Static random access memory device
A technology of static random access and storage devices, which is applied in static memory, digital memory information, semiconductor/solid-state device components, etc., and can solve problems such as limiting scaling capabilities, SRAM array violations of design rule process margins, and consumption
Active Publication Date: 2018-06-05
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
If a reserved area is not formed or not enough reserved area is formed between two directly adjacent SRAM arrays, the SRAM array may violate design rules or have process margin issues
On the other hand, if the reserved area occupies a relatively large area, the reserved area may consume a significant portion of the total space available for fabricating the memory device, and thus will limit scaling capabilities
Method used
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[0019] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may include additional components formed between the first component and the second component An embodiment such that the first part and the second part are not in direct contact. Also, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0020] In ad...
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The embodiment of the invention provides a semiconductor device including a static random access memory (SRAM) device including a first SRAM array including a first plurality of bit cells arranged ina matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts.
Description
technical field [0001] Embodiments of the present invention relate to semiconductor devices, and more particularly, to static random access memory (SRAM) devices. Background technique [0002] SRAM arrays (or macros) typically use edge / strip cells that surround the array of bit cells that store data, such that the outermost bit cells of the SRAM array can have similar environment, thereby creating a more uniform operation of the bitcells regardless of their location in the SRAM array. SRAM arrays forming memory devices generally require reserved areas between adjacent SRAM arrays to separate adjacent SRAM arrays from each other for integration purposes. Reserved regions can also be used for design rule checking purposes. If no reserved area is formed or not enough reserved area is formed between two directly adjacent SRAM arrays, the SRAM array may violate design rules or have process margin issues. On the other hand, if the reserved area occupies a relatively large area,...
Claims
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IPC IPC(8): H01L27/11
CPCH10B10/12H10B10/18H01L23/528H01L23/5226G11C11/412H01L27/0207G11C11/41H10B10/00
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD