Interactive multi-step physical synthesis

Abstract

In one embodiment of the invention, a processor-implemented method is provided for placing and routing a circuit design (102). A first netlist is generated for a circuit design. Placement is performed(108) for the first netlist (106) on a target IC to produce a first placed design (1 10). A set of optimizations are performed (1 12) on the first placed design. The set of optimizations are recorded(1 14) in an optimization history file (1 16). One or more optimizations specified in the optimization history file are performed (1 18 / 202) on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed (206) for the second netlist on the target IC to produce a second placed design (208) that is different than the first placed design. Nets of the second placed design are routed (210) to produce a placed and routed circuit design.

Description

technical field [0001] The present disclosure generally relates to placement, routing, and timing closure of resources in programmable integrated circuits. Background technique [0002] Programmable logic devices (PLDs) are integrated circuits (ICs) used to implement digital logic operations based on user-configurable inputs. Example PLDs include complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs typically contain multiple functional blocks based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transfers signals between functional blocks. [0003] An example FPGA includes an array of configurable logic blocks (CLBs) and rings or columns of programmable input / output blocks (IOBs). CLBs and IOBs are connected to each other through programmable interconnect structures (routing resources). CLBs, IOBs and interconnect structures are typically programmed by loading a stream...

AI Technical Summary

Problems solved by technology

Placing connected elements close to each other also generally improves the performance of the circuit, since long interconnect paths are associated with excess capacitance and resistance, resulting in longer delays

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