A method and system for multi-device cooperative access to SRAM
A multi-device collaboration and device technology, applied in the field of integrated circuits, can solve the problems of increasing circuit area and cost, reducing product market competitiveness, and not being able to guarantee the real-time performance of reading and writing SRAM, achieving good versatility, high real-time performance, and energy saving cost effect
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Embodiment 1
[0040] Embodiment 1: A multi-device cooperative access SRAM system of the present invention specifically includes: MCU, FPGA, and SRAM. Both the MCU and the FPGA need to access the SRAM, and in this embodiment, the priority of the MCU to access the SRAM is higher than that of the FPGA. The FPGA is directly connected to the SRAM, the MCU is connected to the FPGA, and the operation of the MCU to the SRAM is realized by FPGA. The specific steps for MCU and FPGA to access SRAM cooperatively are as follows:
[0041] (3) The FPGA is responsible for managing two registers, one is the SRAM current state register, and the other is the read / write flag register. The SRAM current status register defaults to the idle state. When a device reads / writes the SRAM, the FPGA needs to set the SRAM current status register to the read or write state. After the read / write operation is completed, the SRAM current status register is restored to the idle state. The read / write flag register is in the ...
Embodiment 2
[0044] Embodiment 2: A multi-device cooperative access SRAM system of the present invention specifically includes: MCU, FPGA, and SRAM. The FPGA is the master device, and the MCU is the slave device; both the MCU and the FPGA need to access the SRAM, and in this embodiment, the priority of the FPGA to access the SRAM is higher than that of the MCU. The FPGA is directly connected to the SRAM, the MCU is connected to the FPGA, and the operation of the MCU to the SRAM is realized by FPGA. The specific steps for MCU and FPGA to access SRAM cooperatively are as follows:
[0045] (3) The FPGA controls two flags: one is the current state of the SRAM, and the other is the SRAM read / write flag; the current state of the SRAM is idle by default. When a device reads or writes the SRAM, the FPGA needs to set the current state of the SRAM to the read state or Write state, after the read or write operation is completed, restore the current state of the SRAM to the idle state; the read-write...
Embodiment 3
[0049] Embodiment three: as figure 1 As shown, a system of reliable multi-device cooperative access to SRAM of the present invention consists of: a SRAM read-write device composed of MCU, FPGA, SRAM, RS422 interface circuit, data transmission interface circuit, a data acquisition device installed The upper computer of the device. In the SRAM reading and writing device, both the MCU and the FPGA need to access the SRAM, the FPGA is directly connected to the SRAM, the MCU is connected to the FPGA, and the operation of the MCU to the SRAM is realized through FPGA switching. The MCU needs to write data into the SRAM. In this embodiment, the priority of the FPGA to access the SRAM is higher than that of the MCU. After receiving the read SRAM command, the FPGA needs to read the data in the SRAM without waiting.
[0050] In the described SRAM read-write device, MCU is realized by TM4C1294 of TI Company, and this processor has peripheral interface (EPI), can realize 8 / 16 / 32 parallel ...
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