Low power consumption sigma delta modulator based on capacitance-resistance dual-loop structure

Abstract

The invention discloses a low power consumption sigma delta modulator based on a capacitance-resistance dual-loop structure. The modulator feeds back a quantification result to an input end of each level through SCR DAC1, SCR DAC2 and SCR DAC3, so that ultra-linear adders in a Feed-forward structure are reduced, the design is less complex and the power consumption is reduced. Further, the modulator overcomes defects of high power consumption and poor stability of a traditional CTSD modulator, so that the CTSD ADC is more stable, the same accuracy is realized based on lower power consumption, and the modulator meets the requirements of internet of things.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a low-power sigma delta modulator based on a capacitance-resistance double-loop structure. Background technique [0002] With the development of the times, people have put forward more and more stringent requirements on the power consumption and area of ​​the circuit system. As the link between analog and digital, the power consumption of ADC has attracted much attention. The industry once believed that the pineline ADC was the only choice for applications with high dynamic performance below 100MSPS, but the emergence of continuous time sigma delta (CTSD) ADC subverted people's inherent concepts. The CTSD ADC consists of a CTSD modulator and a digital decimation filter. Compared with the traditional Nyquist ADC, the CTSD ADC does not need the pre-high linearity anti-aliasing filter and the high-speed gain stage required for sampling. Compared with discrete-time sigma de...

AI Technical Summary

Problems solved by technology

In addition, the introduction of ultra-high-speed adders will invisibly bring greater power consumption

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