Method, device and system for writing assembly codes and readable storage medium

Abstract

The invention discloses a method for writing assembly codes. Firstly, by selecting an instruction or an instruction set with the minimum instruction time consumption from alternative instructions, thefunction which needs to be implemented by a program can be achieved with the minimum consumption of CPU cycles; then according to a preset instruction scheduling rule, the target instruction is rearranged so that normal execution of each instruction pipeline can be ensured, and the calculation speed is increased; finally, vectorization is performed on statements without data dependency in the program so that the instruction execution speed can be further increased; at least four pieces of consecutive data are read at a time when the program performs memory access so that the cache hit rate can be increased, and the calculation speed is further increased. According to the provided method for writing the assembly codes, source codes with good initial performance can be obtained, so that theprogram has good performance before being optimized, correspondingly the calculation speed is increased, and the calculation time is shortened. In addition, the invention also discloses a device andsystem for writing the assembly codes and a computer readable storage medium, and the device, the system and the computer readable storage medium all have the effects above.

Description

technical field [0001] The invention relates to the field of computers, in particular to a method, device, system and readable storage medium for compiling assembly codes. Background technique [0002] With the explosive growth of data in various application fields, the time spent on high-performance application computing in this field has also increased exponentially. In order to reduce the calculation time of high-performance applications and improve the timeliness of calculation results, each application can be optimized in two aspects, namely coarse-grained multi-process optimization and underlying optimization that is highly dependent on hardware. [0003] However, in the prior art, since the portability effect of the bottom-layer optimization is poor and the optimization is difficult, the bottom-layer optimization is often ignored. At present, the commonly used low-level optimization method is the SLP (Superword Parallel) vectorization method. This method uses the mem...

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Problems solved by technology

[0003] However, in the prior art, due to the poor portability of bottom-level optimization and the difficulty of optimization, bottom-level optimization is often ignored

At present, the commonly used low-level optimization method is the SLP (Superword Parallel) vectorization method. This method uses the memory access of adjacent addresses as the seed of packaging, and then expands the package heuristically through the definition-use chain and use-definition chain, and finally Using the dependency scheduling package, although making full use of the server's vectorized instructions, it does not take into account the optimization of the hardware instruction pipeline and the impact of memory access on performance, and it is also not suitable for basic blocks and conditional judgment blocks with data dependencies.

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