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Overlay mark and its reliability verification method

A technology of overlay marking and verification method, which is applied in the field of semiconductor manufacturing, can solve the problems of inaccurate measurement of overlay accuracy of thick photoresist, and achieve the effect of improving accuracy

Active Publication Date: 2019-04-26
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The invention provides an overlay mark and its reliability verification method, which is used to solve the problem that the overlay accuracy of the thick photoresist cannot be accurately measured in the prior art, and at the same time realize the reliability of the overlay accuracy measurement, and Verification of Reliability of Overlay Parameter Compensation Value

Method used

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  • Overlay mark and its reliability verification method
  • Overlay mark and its reliability verification method
  • Overlay mark and its reliability verification method

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Embodiment Construction

[0043] The specific implementation of the overlay mark and its reliability verification method provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0044] This specific embodiment provides an overlay mark, with figure 1 It is a structural schematic diagram of an overlay mark in a specific embodiment of the present invention. Such as figure 1 As shown, the overlay mark provided by this specific embodiment includes a first measurement mark 21 (also referred to as a front layer measurement mark) formed in a first layer (also referred to as a front layer) and a A second measurement mark 22 (also referred to as a rear layer measurement mark) in a second layer (also referred to as a rear layer or a current layer), wherein the second layer is formed after the first layer. In some embodiments, the second layer is adjacent to the first layer. In some embodiments, the second measurement marking 22 is visible at the same ...

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Abstract

The invention relates to the technical field of semiconductor device manufacture, and specifically relates to an overlay mark and a reliability verifying method of the same. The overlay mark includesa first measurement mark which is formed in a first layer and includes a plurality of linear type figures, and a second measurement mark which is formed in a second layer and includes a block-shaped figure, wherein the second layer is formed at the back of the first layer; and the projection of the block-shaped figure in the plane of the first measurement mark is located in a closed area enclosedby the straight lines of the plurality of linear type figures. The overlay mark and the reliability verifying method of the same can improve accuracy of thick photoresistive overlay precision measurement, and can effectively solve the problem of thick photoresistive overlay measurement. And at the same time, the overlay mark and the reliability verifying method of the same enable a photoetching craftsman to determine whether the overlay precision between layers accords with the demands and the reliability of the overlay compensation value according to the overlay parameter measurement result.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an overlay mark and a reliability verification method thereof. Background technique [0002] As technology develops, the semiconductor industry is constantly seeking new ways to produce a greater number of memory cells per memory die in a memory device. In non-volatile memory, such as NAND memory, one way to increase memory density is through the use of vertical memory arrays, namely 3D NAND (three-dimensional NAND); with the increasing integration, 3D NAND has moved from 32 layers Developed to 64 layers, or even higher layers. [0003] In the 3D NAND process, the overlay accuracy between each layer of the process is extremely important, especially the overlay accuracy in the step area (Staircase). If there is a positional shift between layers, it will seriously affect the connection between the gate array and the metal wires, which will eventually lead to a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544G06F17/50
CPCG06F30/20G06F2119/18H01L23/544
Inventor 袁文旭方超唐呈前李思晢高志虎冯耀斌
Owner YANGTZE MEMORY TECH CO LTD