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Event-triggered programmable prefetcher

An event and event detection technology, applied in the direction of instrumentation, memory system, program control design, etc., can solve problems such as limitation, pipeline stall, delayed execution, etc.

Active Publication Date: 2022-08-05
ARM LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Preload instructions can prefetch data quickly without using cache capacity in a given environment, or prefetch data slowly and cause delayed execution
In addition, these preload instructions require the address of the target load to be fully computed before being executed, making access to data involving multiple lookup tables often stalling the pipeline and limiting the efficacy of these mechanisms

Method used

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  • Event-triggered programmable prefetcher
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  • Event-triggered programmable prefetcher

Examples

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Embodiment Construction

[0032] figure 1 A part of an integrated circuit 2 comprising a main processor 4 for executing the main program is schematically shown. The main processor 4 is coupled to a level 1 data cache 6 and a level 1 instruction cache 8 (which may be provided with translation lookup buffers (not shown)) which provide the necessary information to be manipulated. value and low-latency access to the program instructions to be executed. Level 1 data cache 6 and level 1 instruction cache 8 are part of the memory architecture (uniformly) coupled to the level 2 cache and further to main memory, and may or may not be formed on the same integrated circuit 2. on an integrated circuit 2.

[0033] Branch prediction circuit 10 generates predicted branch behavior signals for controlling speculative out-of-order execution of program instructions by host processor 4 . The main processor 4 is a relatively high performance and high power consumption processor. The event detection circuit 12 is used t...

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Abstract

The main processor 4 executes the main program and has an associated cache 6 . The event detection circuit 12 detects events caused by the execution of the main program and indicating data to be processed by the main processor. One or more programmable other processors 16 , 18 are triggered by events detected by the event detection circuit 12 to execute other programs. The prefetch circuit 28 triggers the prefetching of data to be used by the host processor into the cache in response to execution of other programs by one or more programmable other processors.

Description

technical field [0001] The present disclosure relates to the field of data processing systems. More specifically, the present disclosure relates to prefetching data (values ​​and / or program instructions to be manipulated) from caches. Background technique [0002] It is known to provide prefetch circuits to prefetch data based on identifying conventional access patterns (eg striding accesses) in memory. However, this prefetch circuit does not work well for unconventional access patterns found in many workloads (eg, pointer tracking, compressed sparse metrics). To achieve better prefetch performance for these workloads, one approach is to embed preload instructions in the program being executed. However, in practice, these preload instructions may be invalidated due to large differences in the execution environment of the program, which may be caused by, for example, the program being executed on different hardware platforms, the hardware platform changing state (eg, on dif...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0862
CPCG06F12/0862G06F2212/1016G06F2212/1044G06F2212/1048G06F2212/6024G06F2212/6026G06F9/3806G06F9/3814G06F12/0875G06F12/1027G06F2212/1021G06F2212/452G06F2212/6022
Inventor 托马斯·克里斯多夫·格鲁卡特萨姆·安斯沃思蒂莫西·马丁·琼斯
Owner ARM LTD