FPGA-based configurable parallel fast convolution kernel structure

A fast convolution and convolution operation technology, applied in neural architecture, physical implementation, biological neural network model, etc., can solve problems such as insufficient real-time requirements for high-speed signals, low speed and efficiency, and achieve convolution operation. Speed ​​improvements, strong encapsulation and stylized, easy to instantiate effects

Inactive Publication Date: 2018-09-04
NANKAI UNIV
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Problems solved by technology

[0003] When facing high-speed signals or having real-time requirements for signal processing, the speed and efficiency of commonly used software convolution algorithms are low, which is not enough to meet the real-time requirements for high-speed signal processing

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  • FPGA-based configurable parallel fast convolution kernel structure
  • FPGA-based configurable parallel fast convolution kernel structure
  • FPGA-based configurable parallel fast convolution kernel structure

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Embodiment Construction

[0015] In order to illustrate the embodiments of the present invention more clearly, the present invention will be further described below with reference to the accompanying drawings.

[0016] When the user needs to increase the speed of the convolution operation by 256 times, 256 configurable parallel fast convolution cores should be instantiated. The serial number register assignment of each core starts from 0 to 255, and the burst length register is set to 256. Due to the excessive number, only a few key positions of the hardware structure of the configured parallel fast convolution kernel are listed: figure 1 Shown is the fast convolution kernel with serial number 0, such as figure 2 Shown is the fast convolution kernel with serial number 127, such as image 3 Shown is the fast convolution kernel with serial number 254, such as Figure 4 Shown is the fast convolution kernel with serial number 255. When the width of the two sequences to be convolved is 12bit and the depth is...

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Abstract

The invention discloses an FPGA-based configurable parallel fast convolution kernel structure. The fast convolution kernel is mainly composed of five registers including a serial number register, a data width register, an address width register, a latch width register and a burst length register, two columns of caches, a multiplier, an adder and a latch in the aspect of hardware structure. According to the fast convolution kernel, the five registers can be flexibly configured by the Verilog program according to the hardware resources of the selected FPGA to realize fast instantiation, and multiple kernels collaborate to perform parallel convolution operation so as to achieve the objective of hardware acceleration of massive convolution operation.

Description

【Technical Field】 [0001] The invention belongs to the field of high-speed digital signal processing. It makes full use of the rich resources of FPGA hardware and the characteristics of parallel operation to design a fast convolution kernel that can be parameterized configuration and multi-core collaborative parallel computing, and performs fast convolution operations on two discrete digital signals. To improve the speed and efficiency of convolution operations. 【Background technique】 [0002] In practical applications such as image processing, digital filtering, time-domain frequency-domain transformation, and spatial positioning, convolution is a commonly used and very important digital signal processing method. [0003] When facing high-speed signals or requiring real-time signal processing, the speed and efficiency of commonly used software convolution algorithms are low, and they are insufficient to meet the real-time requirements for high-speed signal processing. The use of F...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/06G06N3/04
CPCG06N3/063G06N3/045
Inventor 孙桂玲王鹏霄马方舒郑祥雨
Owner NANKAI UNIV
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