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A Test Code Generating Circuit

A technology for generating circuits and test codes, which can be used in the fields of measuring electricity, measuring electrical variables, and testing electronic circuits, and can solve problems such as low reliability and poor safety performance.

Active Publication Date: 2020-11-24
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a test code generation circuit to solve the problems of poor safety performance and low reliability in existing test circuits and methods

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0017] Embodiment 1 provides a test code generation circuit for SOC chip testing. The test code generation circuit includes an N-bit counter, an M-bit shift register, a test mode lock unit, a key judgment lock unit and an output selection unit; wherein, the auxiliary signals entering the test include a reset signal pin0, a first pin signal pin1 , the second pin signal pin2, the third pin signal pin4 and the power-on reset signal Lvr, the reset signal pin0 is valid at low level, the first pin signal pin1 is used to shield the reset signal, the second The pin signal pin2 is used for data input for generating test codes, the third pin signal pin3 is used for clock input for generating test codes, and the power-on reset signal Lvr is used for power-on reset inside the chip. It is ensured that after the chip is powered on and reset inside, when it enters the test mode, the whole chip system is in the reset state, and the test circuit works, which ensures the reliability of the chip...

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PUM

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Abstract

The invention provides a test code generation circuit, and belongs to the technical field of integrated circuits. The test code generation circuit is used for an SOC chip test and includes an N-bit counter, an M-bit shift register, a test mode locking unit, a key determination locking unit and an output selection unit, wherein auxiliary signals entering the test include a reset signal, a first pinsignal, a second pin signal, a third pin signal and a power-on reset signal, and a highest bit of a test code or the reset signal is used as an output condition of the test code. While the test codeis output, a chip system can still be in a reset state or in a non-reset state, thereby improving the reliability of the chip system test.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a test code generating circuit. Background technique [0002] With the popularity of smart wearable devices, smart hardware and the rise of the Internet of Things, SOC chips have been widely used in consumer electronics, industrial control, medical equipment and artificial intelligence, and more and more SOC chips have followed. The integration of different IP cores, including digital IP and analog IP, has led to higher and higher requirements for the testing of SOC chips. [0003] Existing methods for testing SOC chips mainly include the following two categories: 1. The testing of SOC chips usually uses the pins of the chip to perform test enablement, test mode selection, and signal control of functional modules. 2. Use the pins of the chip to test the enable, and then use the common pins of the chip as clock and data input to select the test mode. [0004] Adoptin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2851
Inventor 鲍宜鹏王效
Owner 58TH RES INST OF CETC