A read circuit with redundant structure

A technology of redundant structure and read circuit, applied in the field of memory circuit, can solve problems such as read errors, achieve the effect of reading data accurately and reducing the read error rate

Active Publication Date: 2021-09-24
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
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  • Claims
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Problems solved by technology

However, because the high-speed sense amplifier is very sensitive to the change of CMOS process and the mismatch of the device, the read error will be caused when the device does not match, resulting in a certain read error rate of the sense amplifier.

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  • A read circuit with redundant structure
  • A read circuit with redundant structure

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Embodiment Construction

[0016] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, the following will be described in detail in conjunction with the accompanying drawings and specific embodiments. The description here does not mean that all the subjects corresponding to the specific examples stated in the embodiments are in cited in the claims.

[0017] Please refer to figure 1 , figure 2 , a read circuit with a redundant structure, including a first sense amplifier, a second sense amplifier, a third sense amplifier, a first magnetic tunnel junction MTJ1, a second magnetic tunnel junction MTJ2, a first transistor T1, a second transistor T2 and voting circuits;

[0018] The input terminals of the first sensitive amplifier, the second sensitive amplifier and the third sensitive amplifier are all connected to the chip selection signal end of the memory, and the left and right branches of the first sensitive amplifier, the secon...

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Abstract

The invention discloses a read circuit with a redundant structure, comprising a first sense amplifier, a second sense amplifier, a third sense amplifier, a first magnetic tunnel junction MTJ1, a second magnetic tunnel junction MTJ2, a first transistor T1, a second magnetic tunnel junction Two transistors T2 and a voting circuit; the input ends of the three sensitive amplifiers are all connected to the chip selection signal end of the memory, and the left and right branches of the three sensitive amplifiers respectively pass through the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 and connect with the first magnetic tunnel junction MTJ2. The first transistor T1 and the second transistor T2 are grounded, and the output terminals of the three sensitive amplifiers are connected to the input terminals of the voting circuit; the effect is: by using multiple sensitive amplifiers for current reading and sharing the magnetic tunnel junction, even if a certain sensitive amplifier After the amplifier reads errors, the wrong data can be shielded after passing through the voting circuit, so as to reduce the read error rate and make the read data more accurate.

Description

technical field [0001] The invention belongs to the technical field of memory circuits, and in particular relates to a read circuit with a redundant structure. Background technique [0002] At present, in the general register or random access memory read circuit, most of the amplification part has only one sense amplifier. However, because the high-speed sense amplifier is very sensitive to the change of CMOS process and the mismatch of the device, when the device does not match, it will cause read errors, resulting in a certain read error rate of the sense amplifier. In addition, when it is applied to the magnetic random access memory and combined with the magnetic tunnel junction (MTJ), due to the difference in TMR (tunnel magnetoresistance), the read error rate of the sense amplifier will also be different. Contents of the invention [0003] In order to solve the above problems, the present invention provides a read circuit with a redundant structure, which is used to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/16G11C7/06
CPCG11C7/062G11C11/1673
Inventor 钟智勇曹安琪
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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