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COA array substrate, preparation method thereof and display device

An array substrate and array technology, applied in the fields of COA array substrates, preparation methods and display devices, can solve the problems of ITO residue and lack of planarization, and achieve the effects of reducing conduction resistance, reducing the risk of open circuit, and avoiding crossover

Active Publication Date: 2018-11-02
SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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AI Technical Summary

Problems solved by technology

[0008] In the BPS technology, it is found that at the boundary of the color filter layer (such as figure 2 It is easy to form ITO residue at the corner of the slope (Taper) on the middle boundary 26); and for a class of technology such as an inorganic insulating protective layer, due to the lack of planarization, the ITO pattern on the metal trace may also be too large due to the metal Taper and may break, will introduce adverse effects

Method used

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  • COA array substrate, preparation method thereof and display device
  • COA array substrate, preparation method thereof and display device
  • COA array substrate, preparation method thereof and display device

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Embodiment Construction

[0035] see image 3 , which is a schematic plan view of a preferred embodiment of the COA array substrate of the present invention. The COA array substrate mainly includes: a TFT array arranged on the substrate, including gate lines (not shown) and data lines (not shown), the entire surface is covered with a first insulating protective layer; The color filter layer pattern 22, i.e. RGB color resistance; the color filter layer pattern 22 is dug in the gate line area, and the gate line area is not only provided with a gate line, but also provided with a TFT structure 31 drain electrode or storage For the source and drain metal block patterns 21 of the capacitor, black spacers can be made later, and the color filter layer patterns 22 are connected and overlapped in the data line area; the second insulating protective layer is subsequently deposited, and then the ITO conductive electrode pattern is prepared.

[0036] The ITO conductive electrode pattern mainly includes: the pixel...

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Abstract

The invention relates to a COA array substrate, a preparation method thereof and a display device. The COA array substrate comprises a TFT array and a graphical colored filter layer pattern and is characterized in that the TFT array is arranged on a substrate; the colored filter layer pattern is arranged above the TFT array; the colored filter layer pattern is excavated in a gate line area and isconnected and overlaps in a data line area; DBS public electrode wires are parallelly arranged above a data line; the grid line area is provided with at least one ITO connecting wire which extends along a grid line direction and connects the two adjacent DBS public electrode wires, and each ITO connecting wire is an ITO connecting wire extending along the bottom of the boundary slope of the colored filter layer pattern. The COA array substrate, the preparation method thereof and the display device have the advantages that the ITO connecting wire is arranged at the bottom end of boundary slopeof the colored filter layer pattern, residual boundary terrain can be easily formed by using ITO, stable film forming is achieved, and conductor impedance is lowered; meanwhile, crossing of the ITO connecting wire and metal wires is avoided, and disconnection risk is lowered.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a COA array substrate, a preparation method and a display device. Background technique [0002] In LCD manufacturing, M1 / M2 / ITO (metal layer 1 / metal layer 2 / indium tin oxide) are mainly used as patterned electrode layers. It is necessary to ensure the spacing of film formation patterns in the design and manufacturing process, especially the same layer The safe distance between electrodes of different materials (depending on the size resolution, etc., taking ITO as an example is generally about 5um) to prevent short-circuiting or crosstalk. [0003] At the same time, in addition to the expected results in design and process, the problem of patterning of a certain layer of electrodes often occurs during the manufacturing process, and conductive material residues occur in some non-set areas, which will affect the display quality of the panel depending on the degree. In production ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1362H01L27/12H01L21/77
CPCG02F1/136286G02F1/136295H01L27/124H01L27/1259
Inventor 曹武
Owner SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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