A Method for Optimizing Impedance Discontinuities at High-Speed ​​Link Capacitance

A high-speed link and continuity technology, applied in the server field, can solve problems such as incomplete reference planes, affecting current flow distribution, and affecting signal transmission quality, so as to optimize impedance discontinuity, small impedance changes, and improve signal transmission quality Effect

Active Publication Date: 2021-11-02
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the above design idea can effectively improve the impedance at the capacitor and reduce the impedance discontinuity, hollowing out the reference layer of the capacitor pad will reduce the integrity of the reference plane, affect the flow distribution of the current, and may cause power integrity problems
In addition, if there are other high-speed lines under the capacitor, the reference planes of other high-speed lines will be incomplete, which will affect the quality of signal transmission

Method used

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  • A Method for Optimizing Impedance Discontinuities at High-Speed ​​Link Capacitance
  • A Method for Optimizing Impedance Discontinuities at High-Speed ​​Link Capacitance
  • A Method for Optimizing Impedance Discontinuities at High-Speed ​​Link Capacitance

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Embodiment Construction

[0021] like Figure 1-5 as shown, figure 1 A flow chart of a method for optimizing impedance discontinuity at a high-speed link capacitance proposed by the present invention; figure 2 It is the wiring length diagram of each section of the high-speed link; image 3 It is the simulation diagram of the link time domain reflectometer with the transition area A1 being 80ohm and A2 being 83ohm; Figure 4 It is the link time domain reflectometer simulation diagram of the transition zone A1 is 87ohm, A2 is 90ohm and A1 is 93ohm, A2 is 95ohm; Figure 5 It is a partial enlarged view and impedance measurement of the high-speed link time domain reflectometer.

[0022] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0023] A method of optimizing impedance discontinuity at high-speed link capacitance, comprising the steps of:

[0024] S1: Divide the wiring in the PCIE high-speed link into the outgoing line L1 of ...

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Abstract

The invention discloses a method for optimizing the impedance discontinuity at the capacitance of a high-speed link. The high-speed link includes a main board, and the main board includes a transmitting end, a capacitor and a receiving end; The wiring L2 is connected, and the capacitor is connected to the receiving end through the connecting line L3; the method includes the following steps: adding a transition zone wiring A1 between L2 and the capacitor, and adding a transition zone wiring A2 between the capacitor and L3; adjusting A1 and A2 impedance, and conduct time domain reflectometer simulation for the different impedances of A1 and A2; compare the impedance continuity of the high-speed link when comparing the different impedances of A1 and A2 according to the simulation results; determine the optimal impedance of A1 and A2 according to the comparison results value. In the method disclosed by the invention, the wiring in the transition zone is added before and after the capacitor, and the optimal value of the impedance of the wiring in the transition zone is obtained by simulating the influence of the wiring in the transition zone on the overall characteristics of the link under different impedance conditions.

Description

technical field [0001] The invention relates to the technical field of servers, in particular to a method for optimizing impedance discontinuity at high-speed link capacitance. Background technique [0002] In traditional digital system design, high-speed interconnect phenomena are often negligible because they have little impact on system performance. However, with the continuous development of computer technology, high-speed interconnection is playing a leading role among many factors that determine system performance, which often leads to some unforeseen problems and greatly increases the complexity of system design. Therefore, in the design of high-speed links, it is necessary to optimize each module as much as possible, evaluate the design feasibility and risk points in advance with the help of simulation tools, and optimize the design based on the simulation results to improve the success rate of system design and shorten the development cycle. [0003] In the design ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/32
CPCG06F30/39
Inventor 荣世立
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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