A ldpc code codec multiplexing method suitable for 5g system

Abstract

The present invention relates to an LDPC code codec multiplexing method suitable for 5G systems. For the structure of the LDPC code check matrix in the 5G standard, the coder can be realized by multiplexing some units of the decoder, wherein, for double diagonal In the part, the message bits and the parity bits set to zero are sent to the decoder. Using the syndrome calculation in the first iteration of the decoder, the output syndrome is used as the intermediate variable required for the core array encoding to calculate the check digit, and then the double diagonal partial encoding result can be obtained through the determined logic calculation. For the single-diagonal extension part, the message bits, double-diagonal coded bits and the remaining punctured parity bits to be coded are sent to the decoder, and the decoder continues to perform one iteration, and the parity bits corresponding to the single-diagonal line are iteratively decoded. The code output is the corresponding encoding result. For devices that need to simultaneously implement encoding and decoding functions, the design of the encoder is omitted and the resources consumed by the encoder circuit are reduced.

Description

technical field [0001] The invention relates to an LDPC codec multiplexing method suitable for 5G systems, belonging to the technical field of communication. Background technique [0002] The LDPC code is the Low-Density Parity-Check (LDPC) code, which is a kind of linear block code with a sparse check matrix first proposed by Dr. Robert G. Gallager in 1963. The characteristics of the LDPC code depend on its parity check matrix. The weight of the rows and columns of the check matrix is ​​very small, and it is a very sparse matrix, so it is called low density. The LDPC code can be described by a generator matrix, a corresponding parity check matrix, or a bipartite graph (Tanner graph). [0003] A practical LDPC code parity check matrix is ​​usually a matrix based on a block structure. For a randomly constructed parity check matrix, the complexity of the corresponding encoder and decoder is too high, which leads to difficulties in hardware implementation of LDPC codes and gr...

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Problems solved by technology

Although the BP decoding algorithm has excellent performance, it is relatively complex in hardware implementation, requiring a huge look-up table network to implement logarithmic operations, and consumes a lot of resources; while the minimum sum algorithm has good hardware friendliness, its algorithm is simple to implement, and consumes a lot of hardware resources. Small; a large part of the LDPC code hardware decoder uses the minimum sum decoding algorithm

[0005] For hardware codecs, resource overhead is a major bottleneck limiting LDPC codecs

The huge demand for logic resources and storage resources often becomes the difficulty in designing LDPC code decoders

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