A FPGA-based implementation method for high-speed transmission of multi-channel data 10 Gigabit encryption authentication

Abstract

The invention discloses an FPGA-based method for realizing high-speed transmission of multi-channel data ten-gigabit encryption authentication, which includes the following steps: (1) The Ethernet data transceiver processing module internally forms ten parallel transmissions of 64-bit / 8-bit data according to the configuration requirements channel; (2) use the Ethernet data transceiver processing module as a data distribution platform, configure the key negotiation unit to perform identity authentication and key negotiation operations, obtain session key information in real time and send it to the symmetric encryption and decryption unit synchronously; (3) The symmetric encryption and decryption unit performs encryption and decryption operations on the network message data, and sends them to the 10 Gigabit Ethernet data sending and receiving processing module through the Gigabit Ethernet port. The invention uses the Ethernet online data multi-channel distribution processing mechanism to create multiple data transmission links, enhances concurrent processing capabilities, and concurrently operates through multiple encryption units to improve identity authentication efficiency and data encryption and decryption speed.

Description

technical field [0001] The invention relates to an FPGA-based method for realizing high-speed transmission of multi-channel data ten-gigabit encryption authentication, which belongs to the technical field of network security. Background technique [0002] As the power grid system D5000 is widely deployed in dispatching centers at all levels in China, the remote control system of smart substations and the integrated dispatching system of prefectures and counties are gradually put into use, which puts forward higher requirements for the bandwidth of vertical data transmission channels. Based on the SM1 and SM2 algorithms, the highest bandwidth ciphertext data throughput rate of current mainstream vertical encryption authentication devices is about 1000Mbit / s. In order to further improve the rate and security of data encryption and decryption, and meet the needs of on-site business, a high-performance 10-Gigabit vertical encryption authentication device came into being. [000...

AI Technical Summary

Problems solved by technology

This architecture has high requirements on CPU performance. The software needs to use load balancing technology to realize dynamic and reasonable allocation of resources, and the development depth is limited. The hardware needs to be a non-X86 instruction set multi-core CPU with a main frequency not lower than 1.5GHz. Support, high hardware production costs, single application scenarios, not suitable for market promotion

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