Multi-channel data 10-gigabit encryption authentication high-speed transmission realization method based on FPGA

Abstract

The invention discloses a multi-channel data 10-gigabit encryption authentication high-speed transmission realization method based on FPGA. The method comprises the following steps: (1) forming ten data parallel transmission channels in 64-bit / 8-bit in an Ethernet data transceiving processing module according to a configuration requirement; (2) serving the Ethernet data transceiving processing module as a data distribution platform, configuring to perform identity authentication and key negotiation operation with a key negotiation unit, acquiring session key information in real time and synchronously sending to a symmetric encryption / decryption unit; and (3) performing encryption / decryption operation on network message data through the symmetric encryption / decryption unit, and sending to the 10-gigabit Ethernet data transceiving processing module through a gigabit internet access. Through the method disclosed by the invention, multiple data transmission links are created by using the Ethernet online data multi-channel distribution processing mechanism, the concurrence processing capacity is enhanced, and the identity authentication efficiency and the data encryption / decryption rateare improved through the parallel operation of multiple encryption units.

Description

technical field [0001] The invention relates to an FPGA-based method for realizing high-speed transmission of multi-channel data ten-gigabit encryption authentication, which belongs to the technical field of network security. Background technique [0002] As the power grid system D5000 is widely deployed in dispatching centers at all levels in China, the remote control system of smart substations and the integrated dispatching system of prefectures and counties are gradually put into use, which puts forward higher requirements for the bandwidth of vertical data transmission channels. Based on the SM1 and SM2 algorithms, the highest bandwidth ciphertext data throughput rate of current mainstream vertical encryption authentication devices is about 1000Mbit / s. In order to further improve the rate and security of data encryption and decryption, and meet the needs of on-site business, a high-performance 10-Gigabit vertical encryption authentication device came into being. [000...

AI Technical Summary

Problems solved by technology

This architecture has high requirements on CPU performance. The software needs to use load balancing technology to realize dynamic and reasonable allocation of resources, and the development depth is limited. The hardware needs to be a non-X86 instruction set multi-core CPU with a main frequency not lower than 1.5GHz. Support, high hardware production costs, single application scenarios, not suitable for market promotion

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