Reference current generation circuit for dual sorting grid flash memory

Abstract

The invention discloses a reference current generation circuit for a dual sorting grid flash memory. A memory cell includes a first gate structure and a third gate structure with floating gates, and asecond gate structure therebetween. An array structure is formed by arranging a plurality of memory cells in ranks. A reference current generating circuit is formed by two rows of reference memory cells, and the structure of each reference memory cell is the same as the structure of the memory cell. The first row of reference memory cells output first reference bit line current corresponding to first information storage bits of more than one reference memory cell, and the second row of the reference memory units output second reference bit line current corresponding to second information storage bits of more than one reference memory cell, and the first reference bit line current and the second first reference bit line current are averaged to obtain final reference current. The circuit can reduce adverse effect of reading effect since two different information storage bits of the memory cells are influenced by deviation of a manufacturing process, and improves consistency of the reading effect of the two different information storage bits of the memory cells.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit, in particular to a reference current generating circuit of a double split gate flash memory. Background technique [0002] like figure 1 As shown, it is a structural diagram of a memory cell of the existing dual split gate flash memory; each memory cell 201 includes: a first gate structure 104 , a second gate structure 105 , a third gate structure 106 , and a first source-drain region 102 and the second source and drain regions 103 . [0003] The first gate structure 104 is formed by stacking a first gate dielectric layer 107 , a floating gate 108 , a second gate dielectric layer 109 and a polysilicon control gate 110 formed on the surface of the semiconductor substrate 101 . [0004] The second gate structure 105 is composed of a third gate dielectric layer 111 and a polysilicon gate 112 formed on the surface of the semiconductor substrate 101 . [0005] The second gate structure ...

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Problems solved by technology

[0031] Due to the manufacturing process, the first information storage bit and the second information storage bit are not completely symmetrical, so that the bit line current corresponding to the first information storage bit is not completely consistent with the bit line current corresponding to the second information storage bit, However, the reference current of the existing reference current generation circuit 203a is only related to the reference bit line current corresponding to one of the first information storage bit and the second information storage bit, for example, only the reference bit corresponding to the first information storage bit Line current is related, at this time, the reading operation of the second information storage bit will bring a certain deviation, that is, the reading effect of different information storage bits will be biased, and the following effect is not good

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