Method and system for improving applicability of BJT device mismatch model

Abstract

The invention discloses a method and system for improving the applicability of a BJT device mismatch model. The method comprises the following steps of 1, adding mismatch selection factors mismod in different locating and wiring modes into the mismatch model; 2, according to the mismatch selection factors mismod, selecting different locating and wiring modes for simulation. By means of the methodand system, the applicability of the bipolar transistor BJT device mismatch model can be improved, and the deviation between actual measurement and prediction is reduced.

Description

technical field [0001] The invention relates to the technical field of mismatch models, in particular to a method and system for improving the applicability of mismatch models of BJT devices. Background technique [0002] Currently, the mismatch model of the bipolar transistor (BJT) is a fixed layout mode based on a 1:1 pair structure. In this prior art mismatch model, only the mismatch in a single layout mode is considered, such as figure 1 As shown, the specific parameters are as follows: [0003] mismatch emulation switch misfactor=1, [0004] Currently used bipolar transistor area=4×10 -12 , [0005] The first gain mismatch coefficient bf_0=0.018555, [0006] The first saturation conduction current mismatch coefficient is_0=0.006855, [0007] Gain mismatch random quantity randomb_bf=agauss(1.1,1.0,1), [0008] Saturation conduction current mismatch random quantity randomb_is=agauss(1.1,1.0,1), [0009] gain mismatch [0010] Saturation conduction current misma...

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Problems solved by technology

image 3 It is a schematic diagram of the comparison of the actual measured values ​​of the 1:1 and 1:8 layout and wiring using the mismatch model of the prior art. It can be seen that the deviation between the 1:8 and the 1:1 is obviously large

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