Three-dimensional storage device and method for forming contact hole in step region

Abstract

The invention provides a method for forming a contact hole in a step region of a three-dimensional storage device. The method comprises the following steps of providing a semiconductor structure, wherein the semiconductor structure has a step region, the step region has a plurality of step structures, and each step structure comprises at least one medium layer and at least one conducting layer inalternate stacking from top to bottom; removing a part of conducting layer material from the exposed side wall of at least one conducting layer of each step structure so as to form recessed parts opposite to the adjacent medium layers; covering an insulation layer in the step region; filling each recessed part by the insulation layer; removing the medium layer and the insulation layer on the uppersurface of the step region so as to expose the first conducting layer on the top of each step structure; meanwhile, remaining the insulation layer positioned at each recessed part; forming a second conducting layer on the first conducting layer on the top of each step layer; forming the contact hole on each step structure. The thickness of the conducting layer on the step region is increased, sothat greater allowance can be provided for the etching of the contact hole, so that the contact hole etching penetration probability is reduced.

Description

technical field [0001] The invention mainly relates to a semiconductor manufacturing method, in particular to a method for forming a contact hole in a step region of a three-dimensional memory device, and the three-dimensional memory device. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] In a three-dimensional memory device such as 3D NAND flash memory, a memory array may include a core region and a stair region. The stepped area is used to lead out contacts for the control gates in each layer of the memory array. These control gates are used as word lines of the memory array to perform operations such as programming, erasing and writing, and reading. [0004] In the manufacturing process of 3D NAND flash memory, contact holes are formed...

AI Technical Summary

Problems solved by technology

In the actual production process, due to the large number of steps in the 3D-NAND flash memory, in the contact hole etching step, in order to ensure that the lower steps can be drawn out smoothly, the upper steps are easily over-etched (OverEtch), and etching punch-through (Punch) occurs. Through), resulting in the inability to meet the process requirements and reduce the product yield

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