A semiconductor chip packaging array

Abstract

The present application discloses a semiconductor chip package array, which includes: a lead frame, the lead frame includes: a plurality of matrix-arranged carrying units, a first groove extending from the first surface of the lead frame to the second surface, a first groove extending from the second surface A second groove extending to the first surface, a third groove extending from the second surface to the first surface, wherein the first groove communicates with the second groove to form a through hole, and the third groove connects adjacent The carrying unit; the chip, the chip is arranged on the carrying unit, and is electrically connected with the carrying unit; the plastic sealing layer, the plastic sealing compound wraps the chip and at least part of the carrying unit, and the first groove is filled with the plastic sealing compound to form the plastic sealing layer; electroplating layer, and the electroplating layer is disposed on the second surface of the lead frame and extends into the third groove, or the third groove and the second groove. Through the above method, the present application can increase the area of ​​the pins of the semiconductor package array for soldering to climb.

Description

technical field [0001] The present application relates to the technical field of semiconductor chips, in particular to a packaging array of semiconductor chips. Background technique [0002] With the rapid development of science and technology, the research and development and production of semiconductor chip packaging devices are constantly developing towards the direction of high density, high performance, high reliability and low cost. As a result, the volume of the semiconductor chip packaging device is continuously reduced, the number of pins arranged on the semiconductor chip packaging device is greatly increased, the distance between the pins is getting smaller and smaller, and the density of the pins is getting higher and higher. [0003] The inventors of the present application have found in the long-term research process that in the process of soldering existing semiconductor chip packaging devices (for example, quad flat no-lead package devices, square flat no-lea...

AI Technical Summary

Problems solved by technology

[0003] The inventors of the present application have found in the long-term research process that in the process of soldering existing semiconductor chip packaging devices (for example, quad flat no-lead package devices, square flat no-lead package devices, etc.), soldering often occurs. A case of poor performance because the leads of existing semiconductor packages have only a small area on the bottom for solder to climb

Images