Bonded soi wafer manufacturing method
A manufacturing method and wafer technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., to achieve the effects of increased productivity, high single crystallization, and high versatility
Pending Publication Date: 2018-12-21
SHIN-ETSU HANDOTAI CO LTD
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Problems solved by technology
However, in order to cope with further high-speed, it is gradually necessary to respond to higher radio
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The present invention provides a bonded SOI wafer manufacturing method which comprises: a step for depositing a polycrystalline silicon layer on a base wafer; a step for obtaining a polished surface by polishing the polycrystalline silicon layer; a step for forming an insulating film on a bond wafer; a step for bonding the polished surface of the polycrystalline silicon layer and the bond wafer via the insulating film; and a step for thinning the bond wafer, wherein a single crystal silicon wafer of at least 100 ohm*cm is used as the base wafer, the step for depositing the polycrystalline silicon layer further includes a step for forming, in advance, an oxide film on a surface of the base wafer on which the polycrystalline silicon layer is to be deposited, the polycrystalline silicon layeris deposited by supplying, after being heated to a predetermined temperature of at least 1,000 DEG C, a source gas for the polycrystalline silicon layer at the predetermined temperature, and furthermore, even during heating to the predetermined temperature, the source gas for the polycrystalline silicon layer is supplied. Thus, provided is a bonded SOI wafer manufacturing method in which single crystallization of the polycrystalline silicon layer can be inhibited while high productivity is maintained.
Description
technical field [0001] The invention relates to a method for manufacturing a bonded SOI wafer. Background technique [0002] As an SOI wafer corresponding to a radio frequency (Radio Frequency: RF) device, the solution has been to increase the resistivity of the base wafer to a high resistance. However, in order to cope with the further increase in speed, it is gradually necessary to cope with higher radio frequencies, and it has gradually become impossible to solve it only by using known high-resistance wafers. [0003] Therefore, as a countermeasure, it is proposed to add a layer (carrier trapping layer) that has the effect of eliminating generated carriers immediately below the buried oxide film layer (BOX layer) of the SOI wafer, and it becomes necessary to use A high-resistance polysilicon layer for recombining carriers generated in the high-resistance wafer is formed on the base wafer. [0004] Patent Document 1 describes forming a polysilicon layer or an amorphous s...
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Login to View More IPC IPC(8): H01L21/02H01L21/205H01L27/12
CPCH01L27/12H01L21/76254H01L21/02002
Inventor 若林大士目黑贤二二井谷美保
Owner SHIN-ETSU HANDOTAI CO LTD
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