Bonding contact with cap layer and method of forming same
A capping layer and bonding technology, which is applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve problems such as high cost
Inactive Publication Date: 2019-01-04
YANGTZE MEMORY TECH CO LTD
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
However, as the feature size of semiconductor devices approaches the lower limit, planar processes and fabrication techniques become challenging and costly
Method used
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[0017] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.
[0018] It is noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but It may not be necessary for every embodiment to include that particular feature, structure or characteristic. Furthermore, such phrases are not necessarily referring to the same embodiment. In addition, when a particular feature, structure or characteristic is described in con...
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Abstract
The embodiment of the invention discloses a bonding contact with a cap layer and a method of forming the same. In the embodiment of the invention, a semiconductor device includes a first semiconductorstructure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed over the first device layer and including the first bonding contacts. The second semiconductor structure includes a second device layer,and a second bonding layer disposed under the second device layer and including a second bonding contact. The first bond contact is in contact with the second bond contact at the bond interface. At least one of the first bond contact and the second bond contact includes a cap layer at the bond interface and having a corresponding first bond contact or the remainder of the second bond contact is adifferent conductive material.
Description
Background technique [0001] Embodiments of the present disclosure relate to bonded semiconductor structures and methods of manufacturing the same. [0002] Planar semiconductor devices such as memory cells are scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Three-dimensional (3D) device architectures can address density limitations in some planar semiconductor devices, such as flash memory devices. [0003] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and interconnecting them vertically, for example using through-silicon vias (TSVs) or copper-to-copper (Cu-Cu) connections, such that the resulting structure acts as a single device , resulting in increased performance at reduced power and a smaller fo...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L23/528H01L23/538H01L21/60
CPCH01L23/528H01L23/538H01L24/02H01L24/07H01L2224/08145H01L24/08H01L24/80H01L2224/80895H01L2224/83896H01L2224/80013H01L2224/80011H01L24/83H01L2224/83011H01L2224/83013H01L25/0657H01L2225/06562H01L25/50H01L23/585H01L2225/06541H01L25/16H01L2224/05541H10B43/50H10B43/40H10B43/27H01L24/19H01L24/25H01L24/82H10B43/35
Inventor 潘杰吕术亮马亮李远胡思平万先进
Owner YANGTZE MEMORY TECH CO LTD