Multi-wafer stack structure and forming method thereof

Abstract

The invention provides a multi-wafer stack structure and a forming method thereof. The first dielectric layer and the second dielectric layer are bonded with each other, and the first interconnectionlayer is electrically connected with the second metal layer and the first metal layer through the first opening. The third dielectric layer and the insulating layer are bonded to each other, and the second interconnect layer is electrically connected to the third metal layer and the first interconnect layer through the second opening. The invention eliminates the need for reserving bonding lead space between wafers, eliminates silicon substrate, realizes multi-wafer interconnection and reduces the thickness of multi-wafer stack, thereby reducing the thickness of the whole device after multi-wafer stack packaging, increasing the packaging density and meeting the requirement of increasingly lightweight semiconductor products. Moreover, the semiconductor device no longer needs leads, and thedesign and processing of the silicon substrate and several common pads on the silicon substrate are omitted, which is favorable for reducing the cost and simplifying the process.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a multi-wafer stacking structure and a forming method thereof. Background technique [0002] Under the trend of highly integrated semiconductor development, wire bonding is often used to realize the interconnection between multiple wafers after stacking multiple wafers. Specifically, multiple wafers are stacked vertically on a dedicated silicon substrate. Each wafer has multiple pads for interconnection, and there are multiple common pads on the silicon substrate. One end of the lead is bonded to the pad of the wafer, and the other end of the lead is bonded together. On the common pad of the silicon substrate, the interconnection between multiple wafers is realized. [0003] However, the inventors found that there are some problems in the traditional multi-wafer wire interconnection method: first, there are restrictions on the thickness of mu...

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Problems solved by technology

[0003] However, the inventors found that there are some problems in the traditional multi-wafer wire interconnection method: first, there are restrictions on the thickness of multi-wafer stacking towards high-density development, and space for bonding wires needs to be reserved between multi-wafers that use wire bonding , the silicon substrate itself also has a certain thickness, and to a certain extent, the overall thickness is thicker after multi-wafer stacking; in addition, the lead wire is usually made of gold wire, which has a high cost; in addition, the silicon substrate cannot adapt to the high-density development of multi-wafer stacking. The need for more and more shared pads

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