Semiconductor package structure and manufacturing method

Abstract

The present invention provides a semiconductor package structure and a manufacturing method. The semiconductor package structure includes a substrate, at least one electronic component, an encapsulant, and a redistribution wiring layer. The substrate includes a thermally conductive insulating layer, a patterned circuit layer, and a metal layer. The thermally conductive insulating layer has a firstsurface and a second surface opposite to each other. The patterned circuit layer is disposed on the thermally conductive insulating layer and exposes a portion of the first surface of the thermally conductive insulating layer. The metal layer is disposed on the thermally conductive insulating layer and completely covers the second surface of the thermally conductive insulating layer. The electronic component is disposed on the substrate and electrically connected to the patterned circuit layer. The encapsulant at least covers the electronic component. The redistribution circuit layer is disposed on the encapsulant and electrically connected to the electronic component, wherein the edge of the encapsulant is approximately flush with the edge of the substrate.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure with better heat dissipation effect and a manufacturing method thereof. Background technique [0002] In the existing Quad Flat No-Lead (QFN) package structure, chips are usually disposed on a leadframe. The lead frame has a chip holder and a plurality of pins, and the chip is electrically connected to the pins of the lead frame via bonding wires. These pins, bonding wires and chips are packaged and protected by encapsulant, and the bottoms of these pins are exposed out of the encapsulation material, so as to be electrically connected to an external device such as a printed circuit board. [0003] However, in the aforementioned quad flat no-lead package structure, since the chip needs to be disposed on a lead frame, it is difficult to further reduce the overall thickness of the package structure. Furthe...

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Problems solved by technology

[0003] However, in the above-mentioned quad flat no-lead package structure, since the chip needs to be placed on the lead frame, it is difficult to further reduce the overall thickness of the package structure.

Furthermore, since the quad flat no-lead package structure uses a lead frame as the main structure, no solder is required, so it is difficult to embed passive components such as resistors, capacitors, or inductors that need to be connected by solder in the package structure.

In addition, when the electronic components in the package structure are in operation, a large amount of heat energy will be generated. If the heat energy cannot be dissipated and accumulated continuously, the package structure may be overheated, resulting in performance attenuation or shortened service life. In severe cases, it may even cause permanent damage. damage to

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