Semiconductor electrostatic protection structure
A technology for electrostatic protection and semiconductors, which is applied in the field of semiconductor electrostatic protection structures, and can solve problems such as increased parasitic capacitance
Active Publication Date: 2019-01-15
CSMC TECH FAB2 CO LTD
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Problems solved by technology
As the width of the ESD device increases, its parasitic capacitance will also increase, which will cause fatal problems in high-frequency applications
Method used
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[0034] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0035] figure 2 It is a schematic diagram of a semiconductor electrostatic protection structure. The semiconductor electrostatic protection structure includes a substrate 110, a first well 120 formed on the substrate 110, a second well 130 formed on the substrate 110 and adjacent to the first well 120; The first well 120 is provided with a first doped region 140, the second well 130 is provided with a second doped region 150 and a third doped region 160, and the first well 120 and the second well 130 A fourth doped region 170 is provided at an adjacent position. The first doped region 140, the ...
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The invention relates to a semiconductor electrostatic protection structure, comprising: a substrate; A first well formed on the substrate; A second well formed on the substrate and disposed adjacentto the first well; The first well is provided with a first doping region, the second well is provided with a second doping region and a third doping region, and the positions adjacent to the first well and the second well are provided with a fourth doping region. The first doping region, the fourth doping region, the second doping region and the third doping region are arranged in sequence, and the first doping region and the fourth doping region are isolated from each other, and the second doping region and the third doping region are isolated from each other; The surface of the region between the second doped region and the fourth doped region is provided with a gate structure; Wherein the doping types of the first well and the second well are different; The doping types of the first doping region and the third doping region are the same and different from the doping types of the second doping region and the doping types of the fourth doping region. The semiconductor electrostatic protection structure has small parasitic capacitance and strong electrostatic protection ability.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor electrostatic protection structure. Background technique [0002] Electrostatic discharge is one of the most important reasons for the failure of integrated circuit products. Electrostatic discharge will occur in various links of semiconductor devices or circuits, such as manufacturing, production, packaging, testing, storage, handling and other processes. [0003] Such as figure 1 As shown, the internal circuit of the chip provides its functions to the outside through pins. Among the functional pins of the chip, many are input and output (I / O) pins, and I / O pins are a major source of electrostatic discharge. When electrostatic discharge occurs, the instantaneous high voltage will enter the internal circuit through the I / O pin and damage the internal circuit. [0004] For this reason, a protection circuit is usually set between the internal circuit and ...
Claims
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Login to View More IPC IPC(8): H01L27/02
CPCH01L27/0248H01L27/02
Inventor 孙俊
Owner CSMC TECH FAB2 CO LTD