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Phase locked loop

A phase-locked loop, phase frequency technology, applied in the field of phase-locked loops, can solve problems such as high phase noise

Active Publication Date: 2019-01-15
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, higher PLL bandwidth also results in higher phase noise, which is undesirable for radar systems
This problem is further complicated by the large chirp bandwidth, which increases the rate at which the frequency must reset due to the large difference between the initial frequency and the final frequency

Method used

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Examples

Experimental program
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Effect test

Embodiment Construction

[0043] figure 1 A typical FCMW signal from a conventional FCMW radar system is shown. The signal consists of a number of frequency chirps (only two are shown in the figure), each having an overall duration T 线性调频脉冲 . In each chirp, starting from the initial frequency (f 线性调频脉冲，开始 ) to the final frequency (f 线性调频脉冲，停止 ) to scan frequency. Range information is obtained from the acquisition time 101 of each chirp. During reset time 102 the chirp is reset. Such as figure 1 As shown in , the chirp may also include a dwell time 103 and a settling time 104 .

[0044]The rate of change of frequency during reset time 102 is much higher than in acquisition time 103 to minimize the time loss to reset. Therefore, the reset time 102 is most desirable in terms of the speed and rate of change of the phase-locked loop (PLL) generating the chirp. Thus, the reset time 102 and the rate of frequency change during the reset time 102 determine the bandwidth requirement of the PLL: the shor...

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Abstract

A phase locked loop for generating a linear frequency-modulation pulse is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at afirst input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the linear frequency-modulation pulse at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of thephase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connectedin parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage.

Description

technical field [0001] The present disclosure relates to a phase-locked loop, in particular to a phase-locked loop for generating a frequency chirp. Background technique [0002] Frequency modulated continuous wave (FCMW) radar can be used to determine the range to a target. In contrast to other radar systems such as pulsed radars, FCMW radar systems radiate continuous transmit power. In frequency chirping, the frequency of the emitted radar beam is changed over time. The bandwidth of the chirp (ie, the difference between the lowest and highest transmit frequencies) determines the resolution of the radar system. Systems with larger bandwidths have higher resolution than those with smaller bandwidths. Therefore, to detect nearby objects, a large bandwidth is required, such as 1 GHz or 4 GHz for automotive radar systems. [0003] Frequency chirps have defined rise / fall times, often referred to as acquisition and reset times, respectively. All important information for ran...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/095
CPCH03L7/095H03L7/197H03L7/093G01S7/35H03L7/099
Inventor 塔里克·萨里科
Owner NXP BV