Method and device for distinguishing dynamic capture frames
A technology for distinguishing devices and dynamics, applied in the field of image processing, can solve problems such as inability to distinguish captured frames
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Embodiment 1
[0034] figure 1 A flowchart showing a method for distinguishing dynamic snapshot frames in an embodiment of the present invention, figure 2 A block diagram of a system structure using a method for distinguishing dynamic snapshot frames in an embodiment of the present invention is shown, wherein the method for distinguishing dynamic snapshot frames includes:
[0035] Step S10, obtain the sending time T of the random capture command 0 .
[0036] Obtain the sending time T of the capture command issued by the capture logic 21 to the field programmable gate array 22 (hereinafter referred to as FPGA22) 0 At the same time, the capture logic 21 indirectly controls the image sensor 23 by configuring the field programmable gate array 22, and the image sensor 23 changes the shooting setting to a capture mode. Wherein, the capture logic 21 runs on the processor, and the capture logic 21 determines the working mode of the image sensor 23 : normal capture mode or capture mode. Due to t...
Embodiment 2
[0076] image 3 A structural diagram of a device for distinguishing dynamic capture frames is shown, and the device includes:
[0077] The first obtaining module 301 is used to obtain the sending time T of the random capture command 0 .
[0078] The second acquisition module 302 is used to acquire the transmission start signal time T of the snapshot frame data to be distinguished 1 .
[0079] The third obtaining module 303 is used to obtain the mean value t of the time interval difference between multiple adjacent frame data transmissions n .
[0080] A fourth acquisition module 304, configured to acquire the acquisition completion time T of the frame data to be distinguished 2 .
[0081] The first determination module 305, at T 2 at [T 1 ,T 1 +t n ], it is used to determine the frame data to be distinguished as the snapshot frame to be distinguished.
[0082] Among them, the transmission start signal time T 1 and capture command sending time T 0 The interval is g...
Embodiment 3
[0097] Figure 4 It shows a schematic structural diagram of an electronic device provided by an embodiment of the present invention, the electronic device may include a processor 401 and a memory 404, wherein the processor 401 and the memory 404 may be connected through a bus or in other ways, Figure 5 Take connection via bus as an example.
[0098] The processor 401 may be a central processing unit (Central Processing Unit, CPU). The processor 401 may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or Other chips such as programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above-mentioned types of chips.
[0099] The memory 404, as a non-transitory computer-readable storage medium, can be used t...
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