A SoC system-on-chip and a peripheral bus switch method thereof

Abstract

The invention provides a SoC system-on-chip and a peripheral bus switching method thereof, comprising an AHB bus, an APB bus, a DSP EMIF interface, a DSP address decoding logic, a data interaction unit, an EMIF-AHB / APB bus bridge circuit, AHB slave, APB slave, bus switch controller; The DSP address decoding logic transfers the on-chip access of the DSP to the bus switching controller, the data exchange unit and the EMIF through the access address of the EMIF interface respectively, and transfers the on-chip access of the DSP to the bus switching controller, the data exchange unit and the EMIF-AHB / APB bus bridge circuit. The invention realizes the direct communication between the chip and the off-chip RISC processor, and improves the data communication efficiency. Compared with the on-chipperipherals accessed through the data interaction RAM, it has higher access efficiency. At the same time, on-chip processor core and off-chip DSP form a dual-master mechanism of on-chip peripherals, which makes the system have higher reliability.

Description

technical field [0001] The invention belongs to the field of digital integrated circuit design, and relates to the access of DSP to SoC on-chip peripherals in a SoC+DSP dual-core system, in particular to a SoC on-chip system and a peripheral bus switching method thereof. Background technique [0002] The system on chip has the characteristics of miniaturization, low power consumption, and rich interfaces. In recent years, it has gradually become the control core of computer systems. However, because most of them use RISC processors as the core, their computing power is limited; in computer systems, in order to achieve efficient computing power , Often use the dual-core system of DSP+SoC. SoC is responsible for the control access of system peripherals, and DSP is responsible for complex calculations required by the system. In such a system, data communication between SoC and DSP is required. The common method is to integrate RAM area or asynchronous FIFO that both can access...

AI Technical Summary

Problems solved by technology

In this way, on the one hand, the peripheral data needs to be moved twice, and the real-time performance is poor; on the other hand, both the SoC and the DSP are occupied during the data moving process, which affects the execution efficiency.

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