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Memory read error correction method, system, computer device and storage medium

An error correction and memory technology, applied in error detection/correction, static memory, computing, etc., can solve the problem of low data reading accuracy, achieve the effects of accelerating response speed, reducing consumption, and improving efficiency

Active Publication Date: 2022-07-05
ZHUHAI JIELI TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Based on this, it is necessary to provide a memory reading error correction method, system, computer equipment and storage medium for the above-mentioned problem of low accuracy of data reading in limited bandwidth consumption

Method used

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  • Memory read error correction method, system, computer device and storage medium
  • Memory read error correction method, system, computer device and storage medium
  • Memory read error correction method, system, computer device and storage medium

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Embodiment Construction

[0059] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0060] The memory read error correction method provided by this application can be applied to such as figure 1 In the application environment shown, figure 1 An application environment diagram of the memory read error correction method in one embodiment. The master chip 10 includes a controller 11, the slave chip 20 includes a memory 21, and the controller 11 and the memory 21 are connected through a data bus. The controller 11 can be used to send commands, and can also be used to detect and correct reading errors; the memory 21 can be used to receive commands and gi...

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Abstract

The present application relates to a memory read error correction method, system, computer device and storage medium. The method includes: reading the checksum packet from the memory, dividing the checksum packet into a plurality of sub-checksum packets, and reading the data packet corresponding to the checksum packet in the memory and the current sub-checksum packet in the data packet. Corresponding multi-byte data, the currently read multi-byte data is checked according to the current sub-checksum packet, and when the check of the currently read multi-byte data is judged to be a read error, it will be retrieved from the memory again. Read the multi-byte data corresponding to the current sub-checksum packet, and output the currently read multi-byte data when the check of the currently read multi-byte data determines that the read is correct. Using this method only needs to re-acquire the corresponding multi-byte data when reading the error correction, reducing the data amount of re-reading the correct data, and reducing the bandwidth consumption, so the accuracy of data reading can be improved under the limited bandwidth consumption. sex.

Description

technical field [0001] The present application relates to the technical field of serial peripheral device interface detection, and in particular, to a memory read error correction method, a memory read error correction system, a computer device and a storage medium. Background technique [0002] At present, SPI FLASH (Serial Peripheral Interface flash, read and write serial flash memory), as a high-quality and low-cost storage device, has been applied to various electronic devices. With the continuous innovation of SPI FLASH technology, its reading speed has become faster and faster, resulting in a decline in transmission quality and a greatly increased chance of data errors. [0003] For example, in the process of reading SPI FLASH, taking 32 bytes as the data length of one read as an example, when the controller needs to read the data of SPI FLASH, the controller will send the read command and the read data on the bus. Address, after SPI FLASH receives the command and add...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10G11C29/42
CPCG06F11/1068G11C29/42
Inventor 张锦华
Owner ZHUHAI JIELI TECH
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