Thyristor packaging method

Abstract

The invention discloses a thyristor packaging method. A thyristor comprises a wafer. A number of chips are arranged on the wafer, and external metal disks and lead frames are arranged on the chips. Anumber of fixing points used for fixing the chips and soldering points corresponding to the external metal disks are arranged on the lead frames. The method comprises the steps that the wafer is cut,and the wafer is divided into a number of independent chips; when the chips are pasted, a number of chips are fixed on different fixing points of the lead frames through conductive glue respectively;the conductive glue is heated and cured; at the step of wire bonding, the external metal disks on the chips are connected with the corresponding soldering points on the lead frames through wires; andat the step of packaging molding, the chips and a part of the lead frames are surrounded by a packaging material through injection molding to form a package casing. According to the method, gaps caused by loose combination of the chips, the lead frames and the package casing can be avoided at the step of packaging molding.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a silicon controlled silicon packaging method. Background technique [0002] In the prior art, the thyristor includes a chip and a lead frame, and the packaging is generally completed by machine crimping, argon arc welding, cold sealing and the like. The cold seal is widely used because it requires simple equipment, easy operation, easy maintenance of parts and components, and lower production costs. Cold sealing is to apply sufficient mechanical pressure on the die at room temperature, so that the outer edges of the upper and lower packaging shells can be tightly laminated, thereby achieving the purpose of packaging. However, during the packaging process, due to the gap between the upper and lower package shells at the lead frame, the force on the outer edge of the package may cause the package to warp, which cannot ensure that the chip, lead frame and the upper and lower package ...

AI Technical Summary

Problems solved by technology

However, during the packaging process, due to the gap between the upper and lower package shells at the lead frame, the force on the outer edge of the package may cause the package to warp, which cannot ensure that the chip, lead frame and the upper and lower package shells are tightly combined, leaving gap

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