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A design method of a page-level flash memory conversion layer of a solid-state hard disk

A flash memory conversion layer and design method technology, applied in computing, memory systems, instruments, etc., can solve the problems of reducing the lifespan of NAND flash memory, limited service life, and not supporting in-place updates, etc., to improve overall performance and service life, reduce The effect of write times and good system response time

Active Publication Date: 2019-03-08
HANGZHOU DIANZI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

4) It must be erased before writing data, that is, in-place update is not supported
5) The number of erasing times is limited, exceeding a certain erasing threshold, the overall performance of NAND flash memory will be greatly reduced, that is, the service life is limited
However, due to the continuous change of the mapping items due to the write request, when the changed mapping pair has to be written back to the translation page due to limited RAM space, it will cause frequent updates of the translation page, which will affect the performance of the SSD system and reduce the NAND flash memory. life

Method used

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  • A design method of a page-level flash memory conversion layer of a solid-state hard disk
  • A design method of a page-level flash memory conversion layer of a solid-state hard disk
  • A design method of a page-level flash memory conversion layer of a solid-state hard disk

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0083] Embodiment 1: The write request does not hit in W-CMT and R-CMT.

[0084] Suppose the initial state of the mapped buffer is as Figure 5 As shown in the "initial state" in the figure, there is a request "access data page LPN=1280, write access request, request size 1" arrives, and the processing process is as follows:

[0085] C1, when an access request arrives (LPN=1280), first query the W-CMT, and the request mapping item is not found in the W-CMT, and then query in the R-CMT, and the request mapping item is also not found. At this point, the mapping information of the access request needs to be loaded into the W-CMT.

[0086] C2. At this time, the W-CMT is in a full state, and a mapping item needs to be selected for removal. Since there is no clean mapping information in the priority replacement area, the mapping information (LPN=6) at the LRU position is selected as the victim item (ie, the item to be eliminated).

[0087] C3, through the LPN of the victim item, ...

Embodiment 2

[0096] Embodiment 2: The write request hits in the R-CMT.

[0097] Suppose the initial state of the mapped buffer is as Figure 6 As shown in the "initial state" in "Initial State", there is an existing "access data page LPN=1280, write access request, request size is 1" request arrives, and its processing process is as follows: C1, when an access request arrives (LPN= 1280), query W-CMT first, no request mapping item is found in W-CMT,

[0098] C2 then inquires in the R-CMT, and finds the mapping information corresponding to the request in the R-CMT.

[0099] C3, W-CMT is full at this time, query whether there is a clean mapping item in the priority replacement area, and get a clean mapping item of LPN=833, then remove it as a victim item.

[0100] C4, and then migrate the mapping information from the R-CMT to the MRU position of the W-CMT.

[0101] C5, assuming that the newly allocated data page of the flash memory is PPN=661, update the mapping information, and set the u...

Embodiment 3

[0103] Embodiment 3: The write request hits in the W-CMT.

[0104] Suppose the initial state of the mapped buffer is as Figure 7 As shown in the "initial state" in the figure, there is a request "access data page LPN=1280, write access request, request size 1" arrives, and the processing process is as follows:

[0105] C1, when an access request arrives (LPN=1280), first query the W-CMT, and query the request mapping information in the W-CMT.

[0106] C2. Migrate the mapping information to the MRU position of the W-CMT.

[0107] C3, assuming that the newly allocated data page of the flash memory is PPN=661, update the mapping information, and set the update bit to dirty (Update_flag=1).

[0108] To sum up, the status of the mapping buffer after processing is as follows Figure 7 shown in "End State".

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Abstract

The invention discloses a design method of a page-level flash memory conversion layer of a solid-state hard disk. The invention divides the NAND flash memory into two parts of a data block area and atranslation block area, wherein the data block area is used for storing conventional user data, the translation block area only stores mapping information, and the whole flash memory adopts the page-based mapping. The RAM is divided into W-CMT, R-CMT and GTD three parts. The W-CMT is used for storing write data mapping information with high access frequency. The R-CMT is used to store the read data mapping information with high access frequency, and the GTD is used to record the address mapping entries in the mapping block. The method of the invention realizes the high-flexibility page-level mapping, and at the same time, greatly reduces the frequent updating of translated pages caused by data updating, thereby improving the overall system performance and prolonging the service life of thesolid-state hard disk.

Description

technical field [0001] The invention belongs to the field of firmware optimization design of solid-state hard disks, and in particular relates to a design method for page-level flash memory conversion layers of solid-state hard disks. Background technique [0002] With the rapid development of new-generation information technologies such as cloud computing and mobile Internet, the amount of data has shown an exponential growth, which puts forward higher requirements for data processing and storage. Thanks to the rapid development of semiconductor technology, a solid-state hard disk with NAND as the medium has replaced the traditional hard disk due to its high-speed read and write speed and many other advantages. [0003] Structural characteristics of NAND flash memory: 1) It consists of pages, blocks, and planes nested from small to large. 2) The basic operations are divided into: read, write, and erase. The basic unit of reading and writing is page, and the basic unit of e...

Claims

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Application Information

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IPC IPC(8): G06F12/123
CPCG06F12/125G06F2212/7201G06F12/0246G06F12/123
Inventor 姚英彪颜明博周杰冯维许晓荣刘兆霆
Owner HANGZHOU DIANZI UNIV
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