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A Method of Realizing Parallel CRC in Multi-stage Pipeline Circuit

A flow circuit and electrical connection technology, applied in the field of electronic information, can solve problems such as the inability to increase the operating frequency of the circuit, the inability to insert multi-stage flow water, etc., and achieve the effect of increasing the system data throughput rate and increasing the operating frequency.

Active Publication Date: 2021-04-16
深圳市常茂信科技开发有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the deficiencies of the prior art, the present invention provides a method for realizing parallel CRC in a multi-stage pipeline circuit, which has the advantages of being able to insert multi-level pipeline segmentation combination logic, increasing the operating frequency of the circuit, and achieving the goal of increasing the system throughput rate. Solved the problem that the existing CRC algorithm using LFSR circuit cannot be inserted into multi-stage pipeline and thus cannot increase the operating frequency of the circuit

Method used

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Embodiment

[0044] The LFSR circuit that implements the CRC algorithm such as figure 1 As shown, the CRC calculation result is stored in the DFF. When each clock arrives, the circuit is shifted once, the highest bit is out of the circuit, and the highest bit and the input data are XORed and fed back to the circuit for the next calculation; CRC algorithm polynomial Determine the values ​​of Gk, Gk-1...G1 in the figure. When the value of Gn is 1, the feedback value enters the circuit, otherwise the feedback value does not enter the circuit.

[0045] Take the vector C i and C i+1 Respectively represent the state of the LFSR circuit at time i and time i+1, that is, the value of each DFF, D i Represents the input data at time i, the matrix H represents the coefficient of shift feedback, and the vector L represents the coefficient of data feedback, then the state of the LFSR circuit can be expressed as:

[0046] C i+1 =H·C i +L·D i+1 (Formula 1)

[0047] The above serial method moves 1 ...

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Abstract

A method for implementing parallel CRC in a multi-stage pipeline circuit, splitting the 16-byte data input in each clock cycle into the first 8-byte and second 8-byte data blocks; the first 8-byte data block in each clock cycle The 8 bytes and the second 8 bytes respectively use the CRC32 module to calculate the 8-byte CRC32 result; the 8-byte shift calculation module performs 64 iterative shifts on the calculation results of the first 8-byte CRC32 module; the iterative shift The 64-bit result is XORed with the direct 8-byte CRC32 calculation to obtain the 16-byte CRC32 result of the first clock cycle; the 16-byte shift calculation module converts the 16-byte CRC32 result of the first clock cycle The result is shifted iteratively for 128 times, and the 16-byte CRC32 result of each clock cycle is XORed with the 16-byte CRC32 result of the previous clock cycle after 128 iterative shifts to obtain the final CRC32 of the current clock cycle result. The feedback loop of LFSR is removed, so that multi-stage pipelines can be inserted to increase the system data throughput.

Description

technical field [0001] The invention relates to the technical field of electronic information, in particular to a method for implementing parallel CRC in a multi-stage pipeline circuit. Background technique [0002] At present, the CRC algorithm has been widely used in the communication field as a way of data protection. The CRC algorithm is generally implemented by LFSR in the hardware circuit. There are two methods: serial and parallel. However, LFSR has a feedback loop in the circuit structure, and it is impossible to increase the operating frequency by inserting a multi-stage pipeline, especially when the parallel method is used. When the CRC algorithm is implemented, and the data bit width is large, the combinational logic can reach more than 30 levels. Since the pipeline division combinational logic cannot be inserted, the circuit operating frequency cannot be effectively increased. SUMMARY OF THE INVENTION [0003] (1) Technical problems solved [0004] Aiming at ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00
CPCH04L1/005H04L1/0052
Inventor 李湘琼路远褚艳李玲
Owner 深圳市常茂信科技开发有限公司