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Buffer device, and memory module and memory system each including the buffer device

一种存储器系统、缓冲器装置的技术,应用在存储器系统领域,能够解决信号不足以到达多个存储器装置、高输出阻抗等问题

Active Publication Date: 2019-03-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in a structure in which multiple memory devices are connected to one memory controller, the memory controller has a high output impedance, and therefore, the signal output from the memory controller is insufficient to reach multiple memory devices

Method used

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  • Buffer device, and memory module and memory system each including the buffer device
  • Buffer device, and memory module and memory system each including the buffer device
  • Buffer device, and memory module and memory system each including the buffer device

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Embodiment Construction

[0036] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0037] figure 1 is a block diagram schematically illustrating a memory system 100 according to an embodiment of the inventive concept.

[0038] now refer to figure 1 , the memory system 100 may include a memory controller 120 and a memory module MM. The memory module MM may include a buffer device 140 (or buffer chips) and a plurality of memory devices 160 (or a plurality of memory chips). The buffer device 140 may be connected between the memory controller 120 and the plurality of memory devices 160 . Buffer device 140 may, among other things, provide impedance matching so that the signal output from memory controller 120 is provided with sufficient strength to multiple memory devices.

[0039] The memory controller 120 may control storage operations to the plurality of memory devices 160 . In more detail, the memory controller 120 may trans...

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Abstract

A buffer device, and a memory module and a memory system each including the buffer device are provided. The buffer device includes a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices anda buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signaldelay circuit, and the memory controller performs the training operations by controlling the training block.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Patent Application No. 10-2017-0117232 filed with the Korean Intellectual Property Office on September 13, 2017, the disclosure of which is incorporated herein by reference. technical field [0003] The inventive concept relates to a memory system performing a training operation on a plurality of memory devices, and more particularly, to a buffer device supporting a training operation on a plurality of memory devices, and a memory module and a memory system each including the buffer device. Background technique [0004] Due to the development of memory technology, memory systems for writing and reading large amounts of data are constantly being developed. In this case, a plurality of memory devices are connected to a memory controller included in the memory system in order to control memory operations including write operations and read operations. However, in a structure in ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C7/22
CPCG11C7/1057G11C7/1084G11C7/225G11C5/04G11C29/023G11C29/028G11C7/22G11C7/1093G11C7/222G06F3/0659G06F3/0679G06F3/0604G06F3/0656G06F13/1689G06F13/1668G06F13/1673
Inventor 李将雨任政炖郑秉勋
Owner SAMSUNG ELECTRONICS CO LTD