Three-dimensional computing encapsulation

A three-dimensional, parameter-calculating technology, applied in computing, computers, digital computer components, etc., can solve problems such as being unsuitable for massive computing parameters, slow external memory, and unfavorable processor high-performance computing.

Inactive Publication Date: 2019-04-02
CHENGDU HAICUN IP TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the speed of these external memories is relatively slow, which is not suitable for reading massive calculation parameters, which is very unfavorable for the processor to achieve high-performance computing
The storage of massive computing parameters is increasingly becoming a problem that confuses the industry

Method used

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  • Three-dimensional computing encapsulation
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  • Three-dimensional computing encapsulation

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Embodiment Construction

[0021] The three-dimensional computing (3D-COM) package 300 contains at least one computing chip 100 and at least one memory chip 200 ( Figure 4A-Figure 4C ), which are vertically stacked on each other and electrically coupled through inter-chip connections. The 3D-COM package 300 stores massive calculation parameters in the memory chip 200 inside the package 300 . Viewed from the front of the package 300, the 3D-COM package 300 contains m x n storage units 300aa-300mn ( figure 2 ). The storage unit is the smallest repeating unit of the 3D-COM package 200 . The storage unit is electrically coupled with input 310 and output 320 . Note that a 3D-COM package 300 may contain a large number of storage units 300aa-300mn, which enable massively parallel computing.

[0022] Figure 3A is a perspective view of a storage and calculation unit 300ij. Each storage unit includes a micro-calculation core 180 and at least one storage array 170 . The microcomputing core 180 is formed ...

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Abstract

The invention provides a three-dimensional computing (3D-COM) package which comprises at least one computing chip and at least one storage chip which are vertically stacked and are electrically coupled through inter-chip connection. The 3D-COM package stores a large number of calculation parameters in a storage chip in the package, and the 3D-COM packaging is three-dimensional integration under the microscale, so that the super-large-scale parallel calculation can be achieved, and the calculation efficiency is expected to be greatly improved.

Description

technical field [0001] The present invention relates to the field of integrated circuits, and more specifically, to processor packaging. Background technique [0002] "Computation" is to apply a corresponding law to the input to obtain the output. Figure 1A is an expression of computation. f is the corresponding rule of calculation, also known as a function; P is the parameter that defines the calculation; X is the input data; Y is the output data. X and Y are collectively referred to as calculation data D. The calculation parameter P can have many forms. For example, in artificial intelligence, the calculation parameter is the synaptic weight of neurons; In supercomputing, the lookup table of a function can also be considered as a calculation parameter. Since the parameter P is used to define the calculation, the processor needs to be able to obtain the parameters at high speed during calculation. Therefore, in terms of read speed, the memory requirement for parameter ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78
CPCG06F15/7807
Inventor 张国飙
Owner CHENGDU HAICUN IP TECH
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