Method for packaging multi-laminated multi-chip on flexible circuit board and packaging chipset

Abstract

The invention relates to a method for packaging a multi-laminated multi-chip on a flexible circuit board by adopting FUTCP (Flexible Ultra-thin Three-dimensional Chip Package) and a packaging chipset. Two packaging chips are bound on a middle-layer (bottom) flexible circuit terminal, two packaging chips which are bound on the same symmetrical position of an upper-layer (top) flexible circuit terminal are mutually connected through ACAF (Anisotropic Conductive Adhesives and Films), the chips are stacked, mutually connected and packaged by using NCP (Non-conductive paste), and a chip stacking assembly is packaged by adopting a high-frequency LCP (Liquid Crystal Polymer) chip to bond the multilayer chip and simultaneously solidified; the edge bend of each packaging chip which is connected with the upper-layer (top) flexible circuit is connected with the two middle-layer (bottom) packaging chips in the packaging process so as to form a stacking layer, and the four chips are packaged on the flexible circuit board.

Description

technical field [0001] The invention relates to a multi-stacked multi-chip package, in which a plurality of chips are stacked on a flexible circuit substrate and integrated into a packaged chip group. Specifically, one chip is stacked on top of the other, high-density digital logic devices are integrated and packaged in the middle, and a large-capacity memory is stacked on the top, and conductive connections are made through flexible circuits. technical background [0002] Flexible ultra-thin chip three-dimensional packaging (FUTCP, Flexible ultra-thin chip package), also known as flexible three-dimensional electronic packaging technology, three-dimensional electronic packaging technology, is based on the X-Y plane two-dimensional packaging (referred to as COF packaging), to the three-dimensional direction ( The high-density electronic packaging technology developed by Z-axis) has smaller packaging volume, weight, delay, noise and power consumption, and higher speed and inte...

AI Technical Summary

Problems solved by technology

[0004] In U.S. Patent No. 6,576,992, the chip stacked integrated circuit package uses FBGA (Fine-Pitch Ball Grid Array: Fine-Pitch Ball Grid Array Package, or CSP) technology, because in this patent, the circuit substrate is directly folded when the chip is packaged, so that it is easy to use Substrate wires and packages are damaged, and the time difference between wire signals connecting different chips makes the signals interfere with each other and affects the quality

In US6225688, due to the large difference in the thermal expansion coefficient (CTE) of the flexible substrate, the amount of deformation increases, causing the packaging position of the folded part to not correspond to the mounting point, resulting in the size of the chip package that cannot meet the requirements

[0005] According to this module design package proposed by US6576992 and US6225688, the situation will be worse if more than two chips are packaged or four chips are stacked on one flexible circuit substrate, and it is also impossible to stack one size chip on another size chip, Unable to apply ball grid array packaging technology (FBGA) and chip size packaging technology (FCSP) to the application and development of flexible circuit substrates

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