NAND Flash storage reliability optimization method based on a self-recovery effect

An optimization method and reliable technology, which is applied in the input/output process of data processing, instruments, electrical digital data processing, etc., can solve the problems of decreased insulation capacity of the tunnel oxide layer and reduced reliability of NAND Flash chips, etc., so as to improve the service life , small storage space and low computational complexity

Pending Publication Date: 2019-04-05
HARBIN INST OF TECH
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Problems solved by technology

[0004] After the NAND Flash chip has experienced a large number of P / E operations, because each P / E operation will generate a strong electric field between the floating gate and the substrate, the charges will pass through the tunnel oxide layer, making the originally insulating tunnel oxide layer capture the charge , the insulating ability of the tunnel oxide layer is reduced, and the reliability of the NAND Flash chip is reduced

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  • NAND Flash storage reliability optimization method based on a self-recovery effect
  • NAND Flash storage reliability optimization method based on a self-recovery effect
  • NAND Flash storage reliability optimization method based on a self-recovery effect

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[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0032] The embodiment of the present invention discloses a NAND Flash storage reliability optimization method based on the self-recovery effect, comprising the following steps:

[0033] Step 1: Prepare for data writing operation;

[0034] Step 2: traverse the information storage table and find the data block with the least number of P / E times;

[0035] Step 3: Determine whether the found data block with the least number of P / E times is unique;

[0036] Step ...

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Abstract

The invention discloses an NAND Flash storage reliability optimization method based on a self-recovery effect, which not only considers the P/E times of data blocks, but also preferentially selects the data block with the earliest writing time when the P/E times of the data blocks are equal, so that the residence time of data can be prolonged. The purpose of the invention is to study the change rule of data residence errors of blocks with different wear degrees under different degrees of self-recovery effects by storing P/E times experienced by the data block and storing the last data writingtime of the block, thereby improving the reliability of the NAND Flash.

Description

technical field [0001] The present invention relates to the technical field of solid-state storage, and more specifically relates to a method for optimizing the reliability of NAND Flash storage based on the self-recovery effect. Background technique [0002] Solid State Drives (SSDs) are internally composed of multiple NAND Flash chips. SSDs have excellent characteristics such as strong shock resistance and fast writing speed, and have been widely used in large-scale data centers, personal computers, and mobile storage devices. In order to increase the storage capacity of SSDs and reduce its unit storage cost, NAND Flash has gradually developed from a single-level cell (Single Level Cell, SLC) to a multi-level cell (Multi-level Cell, MLC). Under the same volume, the threshold voltage distance of adjacent states of MLC / TLC will be significantly smaller. [0003] The improvement of the NAND Flash chip production process reduces the unit storage cost and brings high cost per...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
CPCG06F3/0616G06F3/064G06F3/0679
Inventor 魏德宝乔立岩郝梦琪冯骅彭喜元
Owner HARBIN INST OF TECH
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