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Topological partitioning based network-on-chip fast mapping algorithm

An on-chip network and algorithm technology, applied to the mapping problem domain in the on-chip network, which can solve large-scale and accurate solutions to complex problems

Inactive Publication Date: 2019-04-05
曹玲
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The mapping problem belongs to the category of the quadratic allocation problem, and the optimal NoC mapping problem of energy consumption under the bandwidth constraint is solved by using the branch and bound method; but when the NoC scale becomes larger, the execution time of the algorithm increases exponentially, and in limited time and space Medium and large-scale accurate solution is quite complex

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  • Topological partitioning based network-on-chip fast mapping algorithm
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  • Topological partitioning based network-on-chip fast mapping algorithm

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Embodiment Construction

[0013] 1. IP core communication task graph GTC(C, A), in the directed graph GTC, each vertex c i ∈C represents an IP core. Each directed edge a ij ∈A,a ij Indicates that from the IP core c i to IP core c j communication task; weight v(a ij ) represents the communication task a ij data flow, the unit is bit; weight l(a ij ) represents the communication task a ij The maximum transmission delay allowed, expressed in hops.

[0014] 2. Define the NoC architecture graph NAG(R, P), in the directed complete graph NAG, each vertex r i ∈R represents a resource node; each directed edge p ij ∈P,p ij Indicates slave node r i to node r j routing path; weight d(p ij ) means node r i with node r j The routing distance between is represented by the number of hops; the weight e(p ij ) means along the routing path p ij Energy consumption for transmitting 1 bit of data, e(p ij ) = E bit (d(p ij )).

[0015] 3. Given the IP core communication task graph CTG and the NoC architec...

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Abstract

A topological partitioning based network-on-chip fast mapping algorithm is provided. In order to solve the problem of low-energy network-on-chip mapping with communication delay constraints, a topological partitioning based network-on-chip fast mapping algorithm is invented. The algorithm is completed through multiple iterations of the local search and elite reorganization steps, wherein simplified robust tabu search (Ro TS) is used for local search, and COHX cross-operation is used for elite reorganization. The algorithm of the invention has the advantages of good optimization performance, small search space and low energy consumption, and is suitable for solving the problem of large-scale NoC mapping.

Description

Technical field [0001] The invention relates to on-chip network design, in particular to the mapping problem in the on-chip network. Background technique [0002] With the CMOS process stepping into the nanoscale, the number of transistors integrated on a single chip is increasing, and the system-on-chip (SoC) design is becoming more and more complex, and gradually begins to integrate more functional modules. In order to improve the performance, the clock frequency of the processor is also continuously increased, followed by a rapid increase in the power consumption of the chip, leading to the development of the system on chip (SoC) towards the multiprocessor system chip (MPSoC). As more and more IP cores are integrated on a chip, what the chip needs to consider is no longer its own computing power, but gradually shifts its focus to how to deal with the communication between multiple cores. If we still follow the traditional The bus (bus) structure will seriously restrict t...

Claims

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Application Information

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IPC IPC(8): H04L12/933H04L12/24G06N3/12
CPCH04L49/109G06N3/126H04L41/0893
Inventor 曹玲
Owner 曹玲