A clock detection method and device based on a programmable logic device
A technology of programming logic and clock detection, which is applied in the field of communication, can solve the problems of heavy workload and high cost, and achieve the effect of occupying less resources, saving equipment cost and improving stability
Active Publication Date: 2022-04-19
安徽皖兴通信息技术有限公司
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Problems solved by technology
[0003] A clock detection method and device based on a programmable logic device proposed by the present invention can solve the technical problems of heavy workload and high cost in the traditional method of detecting the frequency change direction of the clock
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[0016] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments.
[0017] Based on the problems of error risk and cost increase in existing clock detection methods, embodiments of the present invention provide a clock detection method and device based on programmable logic devices.
[0018] Specifically, the present invention provides a clock detection method and device, which are applied to all electronic equipment using programmable logic devices, such as figure 1 shown, including the following process steps:
[0019] First execute 100, the frequency division module of the measured clock is 8, the specific frequ...
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A clock detection method and device based on a programmable logic device can solve the technical problems of heavy workload and high cost in the traditional method of detecting the frequency variation trend of a clock. It is used on a programmable logic device containing a reference clock, comprising the following steps: obtaining the clock signal of the clock under test, and dividing the clock by eight into the first detection clock; obtaining the reference clock, and using the reference clock The rising edge of the clock is used to collect the first detection clock to obtain the second detection clock; in the high and low level time of the second detection clock, the rising edge of the reference clock is counted respectively; The set parameter value is compared, and the clock state is judged according to the comparison result, and assigned to the register. The present invention can quickly analyze and locate faults through different status indicating signals, thereby improving the stability of equipment. And it takes up less resources, which saves the equipment cost compared with the use of phase-locked links.
Description
technical field [0001] The invention relates to the field of communication technology, in particular to a clock detection method and device based on a programmable logic device. Background technique [0002] At present, with the increasing scale and complexity of communication systems, in order to improve performance and reduce chip power consumption, there are more and more clock domains in the chip, and the number of corresponding clocks is also increasing. In the system Once the quality of the clock signal deteriorates or is lost, it will cause abnormal communication functions. Therefore, it is necessary to detect the accuracy of each clock signal in the system in real time, so as to detect problems early and locate them in time to ensure the stable and normal operation of the entire system. The traditional clock verification method is similar to ordinary signal verification, and the correctness of the clock is verified by purely manual inspection verification and human ...
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Login to View More IPC IPC(8): G06F1/04H04J3/06
CPCH04J3/0644G06F1/04
Inventor 蒋连凤
Owner 安徽皖兴通信息技术有限公司