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Chip package

A chip packaging and chip technology, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems that the thermal resistance of the power module cannot be effectively reduced, and the heat dissipation performance of the power module is affected.

Active Publication Date: 2019-04-16
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the thickness of the ceramic material in the DBC / DPC substrate is about 0.385 mm to 0.635 mm. The thicker thickness will not effectively reduce the thermal resistance of the power module, which will affect the heat dissipation performance of the power module.

Method used

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Examples

Experimental program
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no. 1 example

[0050] Figure 1A is a schematic plan view of a lead frame and a chip in a chip package according to the first embodiment of the present invention, Figure 1B It is a schematic cross-sectional view of a chip package according to the first embodiment of the present invention. Please refer to Figure 1A and Figure 1B , the chip package 10 of this embodiment may include a lead frame 100 , a first chip 210 , a heat dissipation structure 300 and an insulating sealing body 400 . Understandably, in Figure 1A In the schematic plan view of , in order to show the configuration relationship between the lead frame and the chip, the insulating sealing body covering the lead frame and the chip is not drawn. For the arrangement of insulating seals, please refer to Figure 1B cross-sectional schematic diagram, Figure 1B For example along Figure 1A Schematic cross-section of the dotted line A-A. The lead frame 100 includes a die pad 110 and pins 120 connected to the die pad 110 . The ...

no. 2 example

[0061] figure 2 It is a schematic cross-sectional view of a chip package according to the second embodiment of the present invention. Please refer to figure 2 , the chip package 20 of this embodiment is similar to the chip package 10 of the first embodiment, and the same or similar reference numerals represent the same or similar components, so the Figure 1A and Figure 1B The described components will not be repeated here. The difference between the chip package 20 of this embodiment and the chip package 10 of the first embodiment is, for example, that the chip package 20 further includes a printed circuit board (Printed Circuit Board, PCB) 500 . For example, the printed circuit board 500 is located between the die pad 110 of the lead frame 100 and the inner leads 120 a of the leads 120 . The printed circuit board 500 may be connected to the inner pins 120 a through the connecting material 510 and spaced apart from the die pad 110 . For example, the vertical projected ...

no. 3 example

[0064] image 3 It is a schematic cross-sectional view of a chip package according to the third embodiment of the present invention. Please refer to image 3 , the chip package 30 of this embodiment is similar to the chip package 10 of the first embodiment, and the same or similar reference numerals represent the same or similar components, so the Figure 1A and Figure 1B The described components will not be repeated here. The difference between the chip package 30 of this embodiment and the chip package 10 of the first embodiment is, for example, that the chip package 30 of this embodiment includes a first lead frame 610 and a second lead frame 620 connected to the first lead frame 610 . . For example, the first chip 210 and the second chip 220 are both disposed on the first surface 612 of the first lead frame 610 , and the region where the first chip 210 and the second chip 220 are located can be regarded as the chips of the first lead frame 610 seat. The heat dissipat...

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Abstract

A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and tothe outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The thickness of the thermal interface material layer is between 100 Mum and 300Mum. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Description

technical field [0001] The present invention relates to a package structure, and in particular to a chip package. Background technique [0002] Most of the drive control system chips and power module chips of compressors or motor drive control systems in traditional inverter home appliances are packaged by discrete components, and then a single packaged component is assembled on the system board. In order to improve the power density of power components and meet the requirements of low cost, an integrated or intelligent power module (IPM) has been developed, which is characterized by combining a plurality of semiconductor components in a package structure. This provides high output power in a small package structure, thereby increasing power density. For such integrated power modules, the heat dissipation characteristics of the power modules are very important. [0003] Most of the current integrated power modules use a copper-clad ceramic substrate (Direct Bonded Cooper, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/367H01L23/495
CPCH01L23/3114H01L23/367H01L23/495H01L2924/181H01L2224/48091H01L2224/48137H01L2224/73265H01L2224/26175H01L23/4334H01L23/49531H01L23/49575H01L23/3731H01L23/3121H01L2224/32245H01L2224/48247H01L2924/00014H01L2924/00012H01L2924/00H01L23/3157H01L23/4951H01L23/49586
Inventor 高国书张道智陈文志余泰君邱柏凯林彦廷韩伟国
Owner IND TECH RES INST