A high-level verification method applying a UVM verification platform

Abstract

The invention discloses a high-level verification method applying a UVM verification platform, and aims to provide a high-level verification method which has a higher level of verification abstractionlevel and improves the verification efficiency. According to the technical scheme, the high-level verification method applying the UVM verification platform is technically characterized by comprisingthe following steps that the verification platform is started, a TOP layer is called to complete a clock needed by a test platform, and a reset signal and instantiation are generated; The TEST layersends a high-level sequence, the high-level sequence is forwarded to the driver through the sequence generator, the driver extracts corresponding bottom-layer sub-sequences and configuration parameters from the database for sequence initialization, sequence analysis and sequence storage, and then the bottom-layer sub-sequences are sent to the DUT through the virtual interface; The monitor collectsDUT output data and coverage rate data and transmits the collected data to the data collection library, and the scoreboard extracts to-be-compared data from the data collection library and outputs averification result after comparison is completed.

Description

technical field [0001] The invention relates to a high-level verification method using a UVM verification platform based on UVM verification methodology. Background technique [0002] In recent years, with the continuous expansion of the design scale of digital integrated circuits, the workload of chip verification accounts for more than 70% of the chip design cycle. Building a verification platform is the core part of the verification work. It can be said that the verification work efficiency of a verification platform is high or low. , The reusability of components directly determines the success or failure of a chip design. The success rate of a chip tape-out largely depends on the adequacy of verification. Due to the rapid increase in the scale and complexity of chips, this puts forward higher requirements for verification, and the rapid development of chip design and verification technology also makes the requirements for functional verification of modules higher and h...

AI Technical Summary

Problems solved by technology

UVM verification methodology is a mainstream verification methodology in the industry. It mainly verifies the DUT of modules to be verified with similar structures. However, in actual projects, DUT objects of modules to be verified often present multiple interface characteristics. Verification environment, usually in UVM, it is necessary to rebuild the verification environment, establish a connection relationship, and design a hierarchical sequence, so that the complexity of verification and the probability of error increase sharply

[0007] Although the UVM verification methodology is a mainstream verification methodology in the industry, some of the mandatory factory work mode design concepts make it difficult for people to simply use and understand correctly at the beginning, and all verification environment components are integrated. It can only be used, it is difficult to locate the source of the error, and UVM still has difficult data transfer and synchronization problems in the execution process

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