Method for forming three-dimensional memory and three-dimensional memory

Abstract

The invention relates to a method for forming a three-dimensional memory and the three-dimensional memory. The memory comprises a substrate; a first stack and a second stack of stacks on the substrate, wherein the first stack and the second stack respectively comprises spaced gate layers; a plurality of first channel holes in the first stack; a plurality of first channel layers arranged in the plurality of first channel holes; a plurality of second channel holes arranged in the second stack; a plurality of second channel layers arranged in the plurality of second channel holes, wherein each second channel layer corresponds to each first channel layer; and a conductive pattern layer arranged between the first stack and the second stack, wherein the conductive pattern layer comprises a plurality of mutually isolated intermediate conductive parts, each intermediate conductive part is connected with a corresponding first channel layer and a corresponding second channel layer, each intermediate conductive part projects outward from the first channel hole in a radial direction of the first channel hole.

Description

Technical field [0001] The present invention mainly relates to a semiconductor manufacturing method, in particular to a method of forming a three-dimensional memory and a three-dimensional memory. Background technique [0002] In order to overcome the limitation of two-dimensional memory devices, the industry has developed and mass-produced memory devices with a three-dimensional (3D) structure, which increase integration density by arranging memory cells three-dimensionally on a substrate. [0003] In a three-dimensional storage device such as a 3D NAND flash memory, the storage array may include a core region having a channel structure. The channel structure is formed in a channel hole that vertically penetrates the stack of the three-dimensional memory device. The channel holes of the stacked layers are usually formed by a single etching. However, in order to improve storage density and capacity, the number of tiers of three-dimensional memory continues to increase, for exampl...

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Problems solved by technology

However, this method is easy to damage the stacked stacked layers in the wet etching step

And when the upper and lower channel holes are misaligned, the plasma in the process of filling the channel structure can also damage the stacked layers of the stack

In addition, when filling the channel layer and the dielectric layer, it is easy to cause the clogging of the holes, and the introduction of air gaps will affect the performance of the memory cell.

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