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A method and apparatus for analyzing a semiconductor wafer

A semiconductor and wafer technology, applied in the field of defect analysis, can solve problems such as inability to monitor and analyze high defects, and achieve the effect of long-term effective monitoring and analysis

Active Publication Date: 2019-05-03
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0008] As mentioned above, in order to solve the problem that the existing technology cannot effectively monitor and analyze various high defects with different quantities and different distributions, the present invention provides a method for analyzing semiconductor wafers, which is used to analyze the semiconductor wafers to be tested. Defect distribution patterns on a circle, the above methods include:

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  • A method and apparatus for analyzing a semiconductor wafer
  • A method and apparatus for analyzing a semiconductor wafer
  • A method and apparatus for analyzing a semiconductor wafer

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Embodiment Construction

[0069] In the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be apparent, however, to one skilled in the art that the practice of the present invention need not be limited to these specific details. In other words, well-known structures and devices are shown in block diagram form and not in detail in order to avoid obscuring the invention.

[0070] Readers are invited to pay attention to all documents and documents submitted simultaneously with this specification and open to public inspection of this specification, and the contents of all such documents and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, ea...

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Abstract

The invention provides a method and a device for analyzing a semiconductor wafer. The method and the device are used for analyzing a defect distribution mode on a to-be-detected semiconductor wafer. The method comprises the following steps: acquiring a defect distribution map of the to-be-tested semiconductor wafer, wherein the defect distribution map indicates defect distribution in a plane of the to-be-tested semiconductor wafer; establishing a three-dimensional to-be-tested model according to the defect distribution map, the XY plane of the three-dimensional to-be-tested model correspondingto the plane of the to-be-tested semiconductor wafer, and the Z axis of the three-dimensional to-be-tested model corresponding to the number of defects in each grid unit in the XY plane; and calculating the similarity between the three-dimensional to-be-tested model and at least one three-dimensional reference model to determine the defect distribution mode of the to-be-tested semiconductor wafer, each three-dimensional reference model indicating the defect distribution of one mode. Through the above method, intelligent identification and monitoring early warning can be carried out on specialdistribution defects.

Description

technical field [0001] The invention relates to the field of defect analysis, in particular to the defect analysis and monitoring and early warning of semiconductor wafers. Background technique [0002] Defect monitoring and defect analysis has always been one of the indispensable and important links in the semiconductor process flow. Especially in the production process of large-scale integrated circuit wafers, the defect problem generated during the detection process of each process node is a necessary means to control and improve the yield rate. That is to say, how to accurately screen defective semiconductor wafers from many semiconductor wafers is a prerequisite for ensuring subsequent defect analysis, control and improvement of yield. [0003] At present, the industry mainly relies on defect number threshold alarms for online defect monitoring. With the gradual development of semiconductor manufacturing processes, the absolute number of defects has been better control...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T7/00G06T17/00
CPCG06T2207/30148G06T7/001G06T2207/20021G06T2207/20056Y02P90/30G06T19/20G06T2219/2016
Inventor 陈肖宋箭叶何广智
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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