finfet cascode lateral diffusion semiconductor device

Abstract

The present application relates to a finfet cascode lateral diffusion semiconductor device, including a substrate having a first well region including a first dopant and a second well region including a second dopant. The semiconductor device includes semiconductor fin structures formed on a substrate, at least one semiconductor fin structure having a channel region passing through a first well region along a channel axis. A semiconductor device includes a drain region and a source region formed on a semiconductor fin structure. The first well region and the drain region are formed to operate at a first operating voltage, and the second well region and source region are formed to operate at a second operating voltage less than the first operating voltage. The semiconductor device includes a gate structure disposed on a corresponding portion of the semiconductor fin structure and a dummy gate disposed between the gate structure and the drain region. One or more embodiments of the present application address the problem of poorer hot carrier injection that degrades STI quality due to lower temperature annealing, resulting in higher drive current degradation.

Description

Technical field[0001]The applicant generally relates to a semiconductor device, and more specifically, but non-rowless, it involves the FinFET Current Raster Transverse Diffusion Semiconductor Device and Its Making Process.Background technique[0002]As the layout density of the semiconductor device increases, technical proportional scaling has caused development based on fin structure (also known as the FinFET structure) as an alternative to a block metal oxide semiconductor FET structure for improved expandability. The FinFET uses a semiconductor fin to wrap the conductive channel, and the fins form the main body of the transistor. In fact, the gate electrode of the transistor spans or surrounds the fin. During operation, the current flows along the gate side wall surface of the source terminal and the drain terminal.[0003]It has been recognized that many integrated circuits require both low operating voltage FETs (because of their ability to operate with high frequency) and high op...

AI Technical Summary

Problems solved by technology

As laterally-placed technology moves to 7nm and beyond, shallow trench isolation quality deteriorates due to lower temperature anneals, causing worse hot carriers leading to greater drive current degradation (elevated density originating from interference states) injection

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