Termination design for trench superjunction power MOSFET

Abstract

A plurality of trench stripes are disposed in parallel in an epitaxial layer on a drain and extends from a top region to a bottom region of a first surface of the semiconductor. A first polysilicon layer is in each of the trench stripes. The first polysilicon layer extends between the drain and the first surface proximal to the top region and the bottom region, and between the drain and a level below the first surface in a middle region between the top region and the bottom region. A second polysilicon layer is over the first polysilicon layer in the middle region, wherein the first poly silicon layer forms a shield, and the second polysilicon layer forms a gate. A source is in a silicon mesa stripe surrounding the first trench stripe.

Description

technical field [0001] The present disclosure relates generally to power MOSFETs, and more particularly to semiconductor designs for power MOSFETs with improved breakdown voltage characteristics. Background technique [0002] Compared to effect transistors (FETs) with shorter conduction channels, vertical FETs are suitable for high-voltage applications due to their relatively high breakdown voltage. Trench superjunction power metal oxide semiconductor FETs (MOSFETs) are a class of vertical FETs that typically use the reduced surface field (RESURF) effect. RESURF achieves lower on-resistance (RDSon) while still maintaining high breakdown voltage (BVdss). In the case of n-channel FETs (NFETs), in some configurations RESURF is implemented with P-doped pillars in an N-doped epitaxial layer grown over the N+ doped drain. In other configurations, insulating field plates are used instead of P-doped pillars. [0003] In some configurations, the N+ doped drain is an N+ substrate. ...

AI Technical Summary

Problems solved by technology

The on-state resistance of FETs is large due to the high-resistivity epitaxial layers traditionally used to support high breakdown voltages

Images