Structure and formation method of semiconductor device with capacitors

A device structure, capacitor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of increasing the complexity of processing and manufacturing IC, difficult to implement the manufacturing process, and reducing the size of components

Active Publication Date: 2019-05-28
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology

[0004] However, these advances have increased the complexity of handling and manufacturing IC
Manufacturing processes continue to become difficul...
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Method used

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which the first component and the second component are formed in direct contact. An embodiment in which an additional component may be formed between such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and/or characters in various instances. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.
[0068] FIG. 2 is a circuit diagram of a semiconductor device structure according to some embodiments of the present invention. In some embodiments, FIG. 2 shows a corresponding circuit diagram of the semiconductor device structure in FIG. 1J. As shown in FIG. 2, capacitor C1 and capacitor C2 are electrically connected together in parallel. The equivalent capacitance is the sum of the capacitance of the capacitor C1 and the capacitance of the capacitor C2. For example, if capacitor C1 has a capacitance of "A" and capacitor C2 has a capacitance of "B", the equivalent capacitance of capacitors C1 and C2 electrically connected in parallel will be equal to "A+B". Larger capacitances can be realized without taking up too much chip area. In some embodiments, capacitors C1 and C2 are stacked together. Occupies very little die area. The resulting ca...
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Abstract

A semiconductor device structure with capacitors and a formation method thereof are provided. The semiconductor device structure includes a semiconductor substrate and a first capacitor and a second capacitor over the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectriclayer is between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first quadratic voltage coefficient. The second capacitor has a second linear temperature coefficient and a second quadratic voltage coefficient. One or bothof a first ratio of the first linear temperature coefficient to the second linear temperature coefficient and a second ratio of the first quadratic voltage coefficient to the second quadratic voltagecoefficient is negative.

Application Domain

TransistorSemiconductor/solid-state device details +4

Technology Topic

Temperature coefficientEngineering +5

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  • Structure and formation method of semiconductor device with capacitors
  • Structure and formation method of semiconductor device with capacitors
  • Structure and formation method of semiconductor device with capacitors

Examples

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Example Embodiment

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming the first member above or on the second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also be included between the first member and the second member. An additional component may be formed between, so that the first component and the second component may not directly contact an embodiment. In addition, the present invention may repeat reference numerals and/or characters in each example. This repetition is for the purpose of simplicity and clarity, and by itself does not indicate the relationship between the various embodiments and/or configurations discussed.
[0019] Moreover, for ease of description, spatially relative terms such as "below", "below", "lower", "above", and "upper" may be used herein to describe an element as shown in the figure. Or the relationship between a component and another (or other) elements or components. In addition to the orientations shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used here can be interpreted accordingly.
[0020] Some embodiments of the invention are described. Additional operations may be provided before, during, and/or after the stages described in these embodiments. For different embodiments, some of the stages described can be replaced or eliminated. Additional components can be added to the semiconductor device structure. For different embodiments, some components described below can be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in another logical order.
[0021] Figure 1A to Figure 1J These are cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Such as Figure 1A As shown, a semiconductor substrate 100 is received or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate such as a semiconductor wafer. For example, the semiconductor substrate 100 includes silicon or other elemental semiconductor materials such as germanium. In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof. In some embodiments, the semiconductor substrate 100 includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be manufactured using an isolation by injection of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof.
[0022] In some embodiments, isolation features (not shown) are formed in the semiconductor substrate 100 to define and isolate various device elements (not shown) formed in the semiconductor substrate 100. For example, the isolation features include trench isolation (STI) features or local oxidation of silicon (LOCOS) features.
[0023] In some embodiments, various device elements are formed in and/or on the semiconductor substrate 100. Examples of various device elements that can be formed in the semiconductor substrate 100 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors). , High-frequency transistors, p-channel and/or n-channel field effect transistors (PFET/NFET, etc.), diodes, another suitable element, or a combination thereof. Various processes (such as deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof) are performed to form various device elements.
[0024] In some embodiments, such as Figure 1A As shown, a dielectric layer 102 is formed over the semiconductor substrate 100. The dielectric layer 102 may include multiple sub-layers. The dielectric layer 102 may be made of or include the following materials: carbon-containing silicon oxide, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) , Fluorinated silicate glass (FSG), porous dielectric material, another suitable low-k dielectric material, one or more other suitable materials, or a combination thereof.
[0025] In some embodiments, a plurality of conductive features (not shown) are formed in the dielectric layer 102. The conductive components may include conductive contacts, wires, and/or conductive vias. The dielectric layer 102 and the conductive features formed therein are part of an interconnect structure to be formed later. Forming the dielectric layer 102 and forming conductive features in the dielectric layer 102 may involve multiple deposition processes, patterning processes, and planarization processes. The device elements located in and/or on the semiconductor substrate 100 are interconnected by interconnecting structures formed over the semiconductor substrate 100.
[0026] Such as Figure 1A As shown, according to some embodiments, a conductive layer 104 is deposited over the dielectric layer 102. The conductive layer 104 is then patterned to form the lower electrode of the capacitor element. In some embodiments, the conductive layer 104 is made of or includes the following materials: copper, aluminum, gold, titanium, platinum, one or more other suitable materials, or a combination thereof. For example, the conductive layer 104 is made of aluminum copper alloy (AlCu). In some embodiments, the conductive layer 104 has a thickness in a range from about 2000 nm to about 5000 nm. The conductive layer 104 may be deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.
[0027] Such as Figure 1A As shown, according to some embodiments, a barrier layer 106 is deposited over the conductive layer 104. The barrier layer 106 can be used to prevent the metal ions of the conductive layer 104 from diffusing into other material layers to be formed. For example, the barrier layer 106 can prevent the metal ions of the conductive layer 104 from diffusing into the capacitor dielectric layer to be formed on the barrier layer 106.
[0028] The barrier layer 106 may be made of or include the following materials: titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer 106 may have a thickness in a range from about 500 nm to about 800 nm. The barrier layer 106 may be deposited using a PVD process, a CVD process, one or more other suitable processes, or a combination thereof.
[0029] However, many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, the barrier layer 106 is not formed.
[0030] Such as Figure 1A As shown, according to some embodiments, a capacitor dielectric layer 108 is deposited over the barrier layer 106. The capacitor dielectric layer 108 may be made of or include the following materials: oxide materials (such as silicon oxide or germanium oxide), nitride materials (such as silicon nitride or germanium nitride), one or more other suitable materials Materials or their combination. In some other embodiments, the capacitor dielectric layer 108 is made of or includes the following materials: silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, silicon nitride, tantalum oxide, one or more other suitable materials Materials or a combination of them. In some embodiments, the capacitor dielectric layer 108 may be made of or include the following materials: oxide materials with compressive stress. For example, the capacitor dielectric layer 108 may be made of silicon oxide having a compressive stress in the range from about -250 MPa to about -300 MPa. In some other embodiments, the capacitor dielectric layer 108 is made of or includes the following materials: a nitride material with tensile stress. For example, the capacitor dielectric layer 108 may be made of silicon nitride with a tensile stress in the range from about 250 MPa to about 300 MPa. The capacitor dielectric layer 108 may be deposited using a CVD process, a PVD process, an atomic layer deposition (ALD) process, one or more other suitable processes, or a combination thereof. In some embodiments, the capacitor dielectric layer 108 has a To date Thickness within the range. In some embodiments, the capacitor dielectric layer 108 has a To date Thickness within the range.
[0031] After that, like Figure 1A As shown, according to some embodiments, a conductive layer 110 is deposited over the capacitor dielectric layer 108. The conductive layer 110 is then patterned to form electrodes of capacitor elements electrically connected together in parallel. This electrode can be used as the electrode of the lower capacitor element and at the same time as the electrode of the upper capacitor element.
[0032] In some embodiments, the conductive layer 110 is made of or includes the following materials: copper, aluminum, gold, titanium, platinum, one or more other suitable materials, or a combination thereof. For example, the conductive layer 110 is made of aluminum copper alloy (AlCu). In some embodiments, the conductive layer 110 is thinner than the conductive layer 104. In some embodiments, the conductive layer 110 has a thickness in a range from about 300 nm to about 800 nm. The conductive layer 110 may be deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.
[0033] Such as Figure 1A As shown, according to some embodiments, a barrier layer 112 is deposited over the conductive layer 110. The barrier layer 112 may be used to prevent the metal ions of the conductive layer 110 from diffusing into other material layers to be formed. For example, the barrier layer 112 may prevent the metal ions of the conductive layer 110 from diffusing into the capacitor dielectric layer to be formed on the barrier layer 112.
[0034] The barrier layer 112 may be made of or include the following materials: titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer 112 may have a thickness in a range from about 200 nm to about 500 nm. The barrier layer 112 may be deposited using a PVD process, a CVD process, one or more other suitable processes, or a combination thereof.
[0035] However, many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, the barrier layer 112 is not formed.
[0036] Such as Figure 1A As shown, according to some embodiments, a capacitor dielectric layer 114 is deposited over the barrier layer 112. The capacitor dielectric layer 114 may be made of or include the following materials: oxide materials (such as silicon oxide), nitride materials (such as silicon nitride), one or more other suitable materials, or a combination thereof. In some embodiments, the capacitor dielectric layer 114 and the capacitor dielectric layer 108 are made of different materials.
[0037] In some embodiments, the capacitor dielectric layer 114 is made of or includes the following materials: a nitride material with tensile stress. For example, the capacitor dielectric layer 114 may be made of silicon nitride with a tensile stress in a range from about 250 MPa to about 300 MPa. In some other embodiments, the capacitor dielectric layer 114 may be made of or include the following materials: oxide materials with compressive stress. For example, the capacitor dielectric layer 114 may be made of silicon oxide having a compressive stress in a range from about -250 MPa to about -300 MPa. In some embodiments, the capacitor dielectric layer 114 is made of or includes the following materials: a nitride material with tensile stress, and the capacitor dielectric layer 108 is made of or includes the following materials: Oxide material. In some other embodiments, the capacitor dielectric layer 108 is made of or includes the following materials: a nitride material having tensile stress, and the capacitor dielectric layer 114 is made of or includes the following materials: having a compressive stress 的oxide material. In some other embodiments, the capacitor dielectric layer 114 is made of or includes the following materials: silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, silicon nitride, tantalum oxide, one or more other suitable materials Materials or a combination of them. The capacitor dielectric layer 114 may be deposited using a CVD process, a PVD process, an atomic layer deposition (ALD) process, one or more other suitable processes, or a combination thereof. In some embodiments, the capacitor dielectric layer 108 has a To date Thickness within the range. In some embodiments, the capacitor dielectric layer 108 has a To date Thickness within the range.
[0038] After that, like Figure 1A As shown, according to some embodiments, a conductive layer 116 is deposited over the capacitor dielectric layer 114. The conductive layer 116 is then patterned to form electrodes of the capacitor element. In some embodiments, the conductive layer 116 is made of or includes the following materials: copper, aluminum, gold, titanium, platinum, one or more other suitable materials, or a combination thereof. For example, the conductive layer 116 is made of aluminum copper alloy (AlCu). In some embodiments, the conductive layer 116 is thinner than the conductive layer 104. In some embodiments, the conductive layer 116 has a thickness in a range from about 300 nm to about 800 nm. The conductive layer 116 may be deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.
[0039] Such as Figure 1A As shown, according to some embodiments, a barrier layer 118 is deposited over the conductive layer 116. The barrier layer 118 may be used to prevent the metal ions of the conductive layer 116 from diffusing into other material layers to be formed. The barrier layer 118 may be made of or include the following materials: titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer 118 may have a thickness in a range from about 200 nm to about 500 nm. In some other embodiments, the barrier layer 118 is thicker than the barrier layer 112. In some embodiments, the barrier layer 118 will undergo a heavier etching process than the barrier layer 112. Therefore, if the barrier layer 118 has a greater thickness, it is possible to prevent complete etching through the barrier layer 118, which ensures the quality of the semiconductor device structure. The barrier layer 118 may be deposited using a PVD process, a CVD process, one or more other suitable processes, or a combination thereof.
[0040] However, many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, the barrier layer 118 is not formed.
[0041] Such as Figure 1A As shown, according to some embodiments, an anti-reflective layer 120 is deposited over the barrier layer 118. The anti-reflective layer 120 may be used to assist the subsequent patterning process. The anti-reflective layer 120 may be made of or include the following materials: carbon-containing materials (such as polymer materials), nitride materials (such as silicon oxynitride or titanium nitride), one or more other suitable materials, or their The combination. The anti-reflective layer 120 may be deposited using a CVD process, a spin coating process, a spraying process, one or more other suitable processes, or a combination thereof.
[0042] After that, according to some embodiments, such as Figure 1A As shown, a mask layer 122 is formed over the anti-reflection layer 120. The mask layer 122 may be a patterned photoresist layer. The mask layer 122 defines a pattern to be transferred to the conductive layer 116 and the capacitor dielectric layer 114. One or more photolithography processes may be used to form the mask layer 122.
[0043] Such as Figure 1B As shown, according to some embodiments, the anti-reflective layer 120, the barrier layer 118, the conductive layer 116, and the capacitor dielectric layer 114 are partially removed. One or more etching processes can be used to partially remove these layers. As a result, the conductive layer 116 is patterned and used as an upper electrode. The mask layer 122 may be used as an etching mask during one or more etching processes. The one or more etching processes may include a dry etching process, a wet etching process, or a combination thereof. During the etching process for patterning the anti-reflective layer 120, the barrier layer 118, the conductive layer 116, and the capacitor dielectric layer 114, the barrier layer 112 may serve as an etch stop layer.
[0044] Thereafter, in some embodiments, the mask layer 122 is removed after one or more etching processes. In some other embodiments, the mask layer 122 is consumed during one or more etching processes.
[0045] Such as Figure 1C As shown, according to some embodiments, a protective layer 124 is formed over the sidewalls of the capacitor dielectric layer 114, the sidewalls of the conductive layer 116, and the sidewalls of the barrier layer 118. The protective layer 124 can prevent the metal material from being sputtered onto the sidewalls of the capacitor dielectric layer 114, the conductive layer 116, and the barrier layer 118 during the subsequent patterning process. Therefore, short circuits can be prevented or reduced. In some embodiments, such as Figure 1C As shown, the protective layer 124 further extends on the top surface of the barrier layer 112, the sidewalls of the anti-reflection layer 120, and the top surface of the anti-reflection layer 120. In some embodiments, the protective layer 124 is in direct contact with the anti-reflective layer 120, the barrier layer 118, the conductive layer 116, the capacitor dielectric layer 114, and/or the barrier layer 112. In some embodiments, the protective layer 124 extends over these layers in a conformal manner.
[0046] In some embodiments, the protective layer 124 is a single layer. In some other embodiments, the protective layer 124 includes multiple sub-layers. In some embodiments, some of the sub-layers are made of different materials. In some other embodiments, these sublayers are made of the same material. In some embodiments, the protective layer 124 may be made of or include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof. The protective layer 124 may be deposited using a CVD process, an ALD process, one or more other suitable processes, or a combination thereof.
[0047] However, many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, the protective layer 124 is not formed.
[0048] Such as Figure 1D As shown, according to some embodiments, a mask layer 126 is formed over the protective layer 124. The mask layer 126 may be a patterned photoresist layer. The mask layer 126 defines a pattern to be transferred to the conductive layer 110 and the capacitor dielectric layer 108. One or more photolithography processes may be used to form the mask layer 126.
[0049] Such as Figure 1E As shown, according to some embodiments, the barrier layer 112, the conductive layer 110, and the capacitor dielectric layer 108 are partially removed. One or more etching processes can be used to partially remove these layers. As a result, the conductive layer 110 is patterned and used as an intermediate electrode. The mask layer 126 may be used as an etching mask during one or more etching processes. The one or more etching processes may include a dry etching process, a wet etching process, or a combination thereof. During the etching process for patterning the barrier layer 112, the conductive layer 110, and the capacitor dielectric layer 108, the barrier layer 106 may serve as an etch stop layer.
[0050] During one or more etching processes, due to the protective layer 124, the metal material of the conductive layer 110 is prevented from being sputtered on the sidewalls of the capacitor dielectric layer 114, the conductive layer 116, and/or the barrier layer 118 again. Therefore, short circuits can be prevented or reduced. The quality and reliability of semiconductor device structures are improved.
[0051] After that, like Figure 1F As shown, in accordance with some embodiments, the mask layer 126 is removed after one or more etching processes. In some other embodiments, the mask layer 126 is consumed during one or more etching processes.
[0052] Such as Figure 1G As shown, according to some embodiments, a protective layer 128 is formed over the sidewalls of the capacitor dielectric layer 108, the sidewalls of the conductive layer 110, and the sidewalls of the barrier layer 112. The protective layer 128 may prevent the metal material from being sputtered again on the sidewalls of the capacitor dielectric layer 108, the conductive layer 110, and the barrier layer 112 during the subsequent patterning process. Therefore, short circuits can be prevented or reduced. In some embodiments, such as Figure 1G As shown, the protective layer 128 further extends on the top surfaces of the protective layer 124 and the barrier layer 106. In some embodiments, the protective layer 128 is in direct contact with the protective layer 124, the barrier layer 112, the conductive layer 110, the capacitor dielectric layer 108, and/or the barrier layer 106. In some embodiments, the protective layer 128 extends over these layers in a conformal manner.
[0053] In some embodiments, the protective layer 128 is a single layer. In some other embodiments, the protective layer 128 includes multiple sublayers. In some embodiments, some of the sub-layers are made of different materials. In some other embodiments, these sublayers are made of the same material. In some embodiments, the protective layer 128 may be made of or include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof. The protective layer 128 may be deposited using a CVD process, an ALD process, one or more other suitable processes, or a combination thereof.
[0054] However, many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, the protective layer 128 is not formed.
[0055] Such as Figure 1H As shown, according to some embodiments, an anti-reflective layer 129 is deposited over the protective layer 128. The anti-reflective layer 129 may be used to assist the subsequent patterning process. The anti-reflective layer 129 may be made of or include the following materials: carbon-containing materials (such as polymer materials), nitride materials (such as silicon oxynitride or titanium nitride), one or more other suitable materials, or their combination. The anti-reflective layer 129 may be deposited using a CVD process, a spin coating process, a spraying process, one or more other suitable processes, or a combination thereof.
[0056] After that, according to some embodiments, such as Figure 1H As shown, a mask layer 130 is formed over the anti-reflection layer 129. The mask layer 130 may be a patterned photoresist layer. The mask layer 130 defines a pattern to be transferred to the conductive layer 104 and the barrier layer 106. One or more photolithography processes may be used to form the mask layer 130.
[0057] After that, according to some embodiments, the anti-reflection layer 129, the barrier layer 106, and the conductive layer 104 are partially removed. One or more etching processes can be used to partially remove these layers. As a result, the conductive layer 104 is patterned and used as a lower electrode. The mask layer 130 may be used as an etching mask during one or more etching processes. The one or more etching processes may include a dry etching process, a wet etching process, or a combination thereof.
[0058] Such as Figure 1I As shown, in accordance with some embodiments, the mask layer 130 is removed after one or more etching processes. In some other embodiments, the mask layer 130 is consumed during one or more etching processes.
[0059] Such as Figure 1J As shown, according to some embodiments, in Figure 1I A dielectric layer 132 is deposited over the structure shown. The dielectric layer 132 may be made of or include the following materials: carbon-containing silicon oxide, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) , Fluorinated silicate glass (FSG), porous dielectric material, another suitable low-k dielectric material, one or more other suitable materials, or a combination thereof. The dielectric layer 132 may be deposited using a CVD process, an ALD process, a PVD process, a spin coating process, one or more other suitable processes, or a combination thereof.
[0060] After that, like Figure 1J As shown, according to some embodiments, conductive structures 134A, 134B, and 134C are formed in the dielectric layer 132. The conductive structure 134A is electrically connected to the conductive layer 104 (ie, the lower electrode) and the barrier layer 106. The conductive structure 134B is electrically connected to the conductive layer 116 (ie, the upper electrode) and the barrier layer 118. The conductive structure 134C is electrically connected to the conductive layer 110 (ie, the intermediate electrode) and the barrier layer 112. In some embodiments, the conductive structures 134A, 134B, and 134C are conductive vias.
[0061] In some embodiments, the conductive structures 134A, 134B, and 134C are made of or include the following materials: copper, tungsten, aluminum, cobalt, titanium, gold, platinum, one or more other suitable materials, or combinations thereof . In some embodiments, one or more photolithography processes and etching processes are used to form via holes exposing the barrier layers 106, 118, and 112. In some embodiments, because the barrier layer 118 is thicker than the barrier layer 112, the conductive layer 116 located under the barrier layer 118 is prevented from being damaged during the etching process for forming the via. In some other embodiments, one or some of the through holes further expose the conductive layer under the barrier layer.
[0062] After that, the through holes are filled with one or more conductive materials to form conductive structures 134A, 134B, and 134C. The conductive material may be formed using a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.
[0063] In some embodiments, the barrier layer is formed before the conductive material is formed. The barrier layer may be used to prevent metal ions of the conductive material from diffusing into the dielectric layer 132. The barrier layer may be made of or include the following materials: titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer can be deposited using a PVD process, a CVD process, one or more other suitable processes, or a combination thereof.
[0064] However, many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, no barrier layer is formed.
[0065] Such as Figure 1J As shown, according to some embodiments, a conductive structure 136 is formed over the dielectric layer 132. The conductive structure 136 electrically connects the conductive structure 134A and the conductive structure 134B. In some embodiments, the conductive structure 136 is a wire. The conductive structure 136 is made of or includes the following materials: copper, tungsten, aluminum, cobalt, titanium, gold, platinum, one or more other suitable materials, or a combination thereof. The formation of the conductive structure 136 involves a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.
[0066] In some embodiments, a conductive structure 136 is formed in the trench of the dielectric layer. In some embodiments, a dual damascene process is used to form conductive structure 136 and conductive structures 134A, 134B, and 134C in the dielectric layer.
[0067] In some embodiments, conductive layer 104, capacitor dielectric layer 108, and conductive layer 110 together form capacitor C 1 part. In some embodiments, conductive layer 110, capacitor dielectric layer 114, and conductive layer 116 together form capacitor C 2 part. In some embodiments, capacitor C 1 And capacitor C 2 The conductive structures 134A, 136, 134B, and 134C are electrically connected together in parallel.
[0068] figure 2 It is a circuit diagram of a semiconductor device structure according to some embodiments of the present invention. In some embodiments, figure 2 show Figure 1J Corresponding circuit diagrams of the semiconductor device structure in. Such as figure 2 As shown, capacitor C 1 And capacitor C 2 Connect electrically in parallel. The equivalent capacitance is capacitor C 1 The capacitance and capacitor C 2 The sum of capacitance. For example, if capacitor C 1 Has a capacitance of "A" and a capacitor C 2 With a capacitance of "B", then the capacitor C connected in parallel 1 And C 2 The equivalent capacitance of will be equal to "A+B". A larger capacitance can be realized without taking up too much chip area. In some embodiments, capacitor C 1 And C 2 Stacked together. The occupied die area is very small. By using the same area on the wafer, the obtained capacitance can be improved (or even doubled).
[0069] In some embodiments, the capacitance of the capacitor depends on the operating temperature. At different operating temperatures, the capacitance of the same capacitor may be different. The capacitor has a temperature coefficient. The temperature coefficient can be obtained by measuring the capacitance at different operating temperatures, and then fitting the equation as follows:
[0070] C(T)=C T (0)x[1+(T x A T )+T 2 x B T )],
[0071] Among them, "C(T)" is the specific capacitance at a given operating temperature, and "C T (0)" is the capacitance of the capacitor when the operating temperature is 25℃, "A T "Is the linear temperature coefficient, and "B T "Is the square temperature coefficient. In some embodiments, the linear temperature coefficient (A T ) Is much larger than the square temperature coefficient (B T ).
[0072] Capacitor dielectric layers with different materials may have different linear temperature coefficients. In some embodiments, the capacitor dielectric layer is an oxide material with compressive stress (such as silicon oxide with compressive stress). In these cases, the above-mentioned capacitors with capacitor dielectric layers have a negative linear temperature coefficient. Figure 3A The capacitance of capacitors according to some embodiments at different operating temperatures is shown. In some embodiments, the capacitance of the capacitor decreases as the operating temperature increases. The linear temperature coefficient is negative.
[0073] In some other embodiments, the capacitor dielectric layer is a nitride material with tensile stress (such as silicon nitride with tensile stress). In these cases, the above-mentioned capacitors with capacitor dielectric layers have a positive linear temperature coefficient. Figure 3B The capacitance of capacitors according to some embodiments at different operating temperatures is shown. In some embodiments, the capacitance of the capacitor increases as the operating temperature increases. The linear temperature coefficient is positive.
[0074] In some embodiments, the capacitance of the capacitor depends on the applied voltage. Under different operating voltages, the capacitance of the same capacitor can be different. The capacitor has a voltage coefficient. The voltage coefficient can be obtained by measuring the capacitance under different operating voltages, and then fitting the equation as follows:
[0075] C(V)=C V (0)x[1+(V x A V )+V 2 x B V )],
[0076] Among them, "C(V)" is the specific capacitance under a given operating voltage, and "C V (0)" is the capacitance of the capacitor when the operating voltage is 0 volts, "A V "Is the linear voltage coefficient, and "B V "Is the square voltage coefficient.
[0077] Capacitor dielectric layers with different materials can have different square voltage coefficients. In some embodiments, the capacitor dielectric layer is an oxide material with compressive stress (such as silicon oxide with compressive stress). In these cases, the aforementioned capacitors with capacitor dielectric layers have a negative square voltage coefficient. Figure 4A The capacitance of capacitors according to some embodiments at different operating voltages is shown. The square voltage coefficient is negative.
[0078] In some other embodiments, the capacitor dielectric layer is a nitride material with tensile stress (such as silicon nitride with tensile stress). In these cases, the aforementioned capacitors with capacitor dielectric layers have a positive square voltage coefficient. Figure 4B The capacitance of capacitors according to some embodiments at different operating voltages is shown. The squared voltage coefficient is positive.
[0079] The material and/or stress of the capacitor dielectric layer can determine the linear temperature coefficient and squared voltage coefficient of the capacitor. As mentioned above, in some embodiments, the capacitor C 1 The capacitor dielectric layer 108 and capacitor C 2 The capacitor dielectric layer 114 is made of different materials. In some embodiments, the capacitor dielectric layer 108 is made of or includes the following materials: an oxide material with compressive stress (such as silicon oxide with compressive stress) and the capacitor dielectric layer 114 is made of or includes the following materials The following materials: nitride materials with tensile stress (such as silicon nitride with tensile stress). Therefore, the capacitor C 1 It has a negative linear temperature coefficient and/or a negative square voltage coefficient. Capacitor C 2 It has a positive linear temperature coefficient and/or a positive square voltage coefficient.
[0080] In some embodiments, capacitor C 1 Has a negative linear temperature coefficient, and capacitor C 2 Has a positive linear temperature coefficient. Capacitor C 1 The linear temperature coefficient of the capacitor C 2 The ratio of the linear temperature coefficient is negative. Similar to Figure 3A with Figure 3B The ones shown, capacitor C 1 The capacitance can be reduced as the operating temperature increases, and the capacitor C 2 The capacitance can increase as the operating temperature increases. Capacitor C can be added 2 To compensate capacitor C 1 The loss of capacitance. In some other cases, if the operating temperature decreases, you can increase the capacitor C 1 To compensate capacitor C 2 The capacitance loss. Therefore, the capacitor C can still be maintained 1 And C 2 The total equivalent capacitance. Even if the operating conditions change, the reliability and performance of the semiconductor device structure can be maintained.
[0081] In some embodiments, capacitor C 1 Has a negative squared voltage coefficient, and capacitor C 2 Has a positive square voltage coefficient. Capacitor C 1 The square voltage coefficient and capacitor C 2 The ratio of the squared voltage coefficient is negative. Similar to Figure 4A with Figure 4B The ones shown when capacitor C 1 With relatively high capacitance at a given operating voltage, capacitor C 2 Has a relatively low capacitance. When capacitor C 1 With a relatively low capacitance at a given operating voltage, the capacitor C 2 Has a relatively high capacitance. Capacitor C 1 And C 2 It can compensate each other under different operating voltages. Even if the operating conditions change, the reliability and performance of the semiconductor device structure can be maintained.
[0082] Many changes and/or modifications can be made to the embodiments of the present invention. In some other embodiments, the capacitor dielectric layer 114 is made of or includes the following materials: an oxide material with compressive stress (such as silicon oxide with compressive stress) and the capacitor dielectric layer 108 is made of or The following materials are included: nitride materials with tensile stress (such as silicon nitride with tensile stress). Therefore, the capacitor C 2 It has a negative linear temperature coefficient and/or a negative square voltage coefficient. Capacitor C 1 It has a positive linear temperature coefficient and/or a positive square voltage coefficient.
[0083] In some embodiments, each of the capacitor dielectric layers 108 and 114 is a single layer. However, the embodiment of the present invention is not limited to this. Many changes and/or modifications can be made to the embodiments of the present invention. In some embodiments, at least one of the capacitor dielectric layers 108 and 114 has multiple sublayers.
[0084] Figure 5 Is a cross-sectional view of a capacitor dielectric layer of a capacitor according to some embodiments. In some embodiments, the capacitor dielectric layer 108 has multiple sub-layers. In some embodiments, the capacitor dielectric layer 108 has two sublayers 108a and 108b. In some embodiments, the sub-layers 108a and 108b are made of different materials. In some embodiments, the sub-layer 108a may be made of or include the following materials: oxide materials with compressive stress. In some embodiments, the sub-layer 108b may be made of or include the following materials: a nitride material with tensile stress. In some other embodiments, the sub-layer 108a may be made of or include the following materials: a nitride material with tensile stress. In some other embodiments, the sub-layer 108b may be made of or include the following materials: oxide materials with compressive stress. The sub-layers 108a and 108b can compensate each other. Therefore, even if the operating conditions change, the reliability and performance of the semiconductor device structure can be maintained. In some other embodiments, the sub-layers 108a and 108b are made of silicon oxynitride with different compositions. For example, the sub-layer 108a may have a greater concentration of nitrogen atoms than the sub-layer 108b. In some other embodiments, the sub-layers 108a and 108b are made of tantalum oxide with different compositions.
[0085] Image 6 Is a cross-sectional view of a capacitor dielectric layer of a capacitor according to some embodiments. In some embodiments, the capacitor dielectric layer 114 has multiple sublayers including sublayers 114a and 114b. In some embodiments, the sub-layers 114a and 114b are made of different materials. The sub-layers 114a and 114b can compensate each other. Therefore, even if the operating conditions change, the reliability and performance of the semiconductor device structure can be maintained. In some embodiments, both capacitor dielectric layers 108 and 114 have multiple sublayers.
[0086] Figure 7 Is a cross-sectional view of a capacitor dielectric layer of a capacitor according to some embodiments. In some embodiments, Figure 1A-Figure 1J The capacitor dielectric layer 108 (or 114) of has more than two sublayers including sublayers 108a, 108b, 108c, and 108d. In some embodiments, two or more of the sublayers 108a-d are made of different materials. These sub-layers 108a-d can compensate each other. Therefore, even if the operating conditions change, the reliability and performance of the semiconductor device structure can be maintained.
[0087] Many changes and/or modifications can be made to the embodiments of the present invention. In some embodiments, one or more of the conductive layers 104, 110, and 116 are formed to have a smaller average particle size. In some embodiments, the conductive layers 104, 110, and 116 are formed using a sputtering process. In some cases, the sputtering power is about 2.7 kW, and the operating temperature is about 270°C. However, the average particle size of the conductive layers 104, 110, and 116 obtained under the above process conditions may be as large as about 7.4 nm. In order to form a conductive layer with a smaller average particle size, the process conditions are fine-tuned. In some embodiments, higher sputtering power and lower operating temperature are used to constrain the growth of grains in the conductive layer. In some embodiments, the sputtering power is increased to a range from about 9 kW to about 15 kW, and the operating temperature is decreased to a range from about 100°C to about 150°C. In some embodiments, the conductive layers 104, 110, and 116 are cooled immediately after the sputtering process. For example, after the conductive layers 104, 110, and 116 are formed, a water cooling system is used to cool the operating temperature more effectively. Since the temperature of the conductive layers 104, 110, and 116 is lowered in a short time, the grain growth of the conductive layers 104, 110, and 116 is restricted. As a result, each or one of the formed conductive layers 104, 110, and 116 may have a smaller average particle size. In some embodiments, the average particle size ranges from about 3.5 nm to about 6.5 nm. The average particle size can be measured using an atomic force microscope (AFM). The average particle size may be further reduced. In some embodiments, if the average particle size is reduced, the capacitor may have a larger breakdown voltage. For example, the breakdown voltage can be increased from about 25V to a range from about 27V to about 28V. Therefore, due to the smaller average particle size of the conductive layers 104, 110, and 116, the reliability and performance of the semiconductor device structure are improved. In some other cases, if the average particle size of the conductive layer is greater than about 6.5 nm, the breakdown voltage may be lower (such as about 25V).
[0088] In some embodiments, the average particle size of the conductive layer is reduced from about 7.4 nm to about 6.1 nm. . The corresponding breakdown voltage increases from about 25V to about 27V to 28V.
[0089] Many changes and/or modifications can be made to the embodiments of the present invention. In some embodiments, one or more of the barrier layers 106, 112, and 118 are formed to have a smaller average particle size. In some embodiments, the barrier layers 106, 112, and 118 are formed using a PVD process. The air flow used in the PVD process is fine-tuned so that a barrier layer with a smaller particle size can be formed. In some embodiments, the flow rate of nitrogen gas is increased to, for example, 150 sccm. In some embodiments, argon is not used during the formation of barrier layers 106, 112, and/or 118. As a result, each or one of the barrier layers 106, 112, and 118 formed may have a smaller average particle size. In some embodiments, the average particle size ranges from about 0.5 nm to about 1.2 nm. The average particle size can be measured using AFM. In some cases, by fine-tuning the process conditions for forming the barrier layers 106, 112, and 118, the average particle size can be reduced from about 1.78 nm to about 0.92 nm. In some embodiments, if the average particle size is reduced, the barrier layer may have a more uniform thickness. May reduce or prevent capacitance mismatch between nearby capacitors. Therefore, the reliability and performance of the semiconductor device structure are improved. In some other cases, if the average particle size of the barrier layer is greater than about 1.2 nm, the capacitance mismatch between nearby capacitors may be too high.
[0090] The embodiment of the present invention forms a semiconductor device structure having stacked capacitor elements electrically connected in parallel. By choosing capacitor dielectric layers with different materials, capacitor elements can have different linear temperature coefficients and/or squared voltage coefficients. Therefore, the capacitor elements can compensate each other under different operating conditions. Under different operating conditions (such as at different operating temperatures and/or different operating voltages), the total equivalent capacitance may still be approximately the same. Even if the operating conditions change, the reliability and performance of the semiconductor device structure can be maintained.
[0091] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, and a first capacitor and a second capacitor located above the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectric layer is located between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first squared voltage coefficient. The second capacitor has a second linear temperature coefficient and a second squared voltage coefficient. One or both of the first ratio of the first linear temperature coefficient to the second linear temperature coefficient and the second ratio of the first squared voltage coefficient to the second squared voltage coefficient is negative.
[0092] In the above semiconductor device structure, wherein the first capacitor dielectric layer includes a nitride material, and the second capacitor dielectric layer includes an oxide material.
[0093] In the above semiconductor device structure, wherein the first capacitor dielectric layer includes an oxide material having compressive stress, and the second capacitor dielectric layer includes a nitride material having tensile stress.
[0094] In the above semiconductor device structure, wherein at least one of the first capacitor dielectric layer and the second capacitor dielectric layer has a plurality of sublayers, and at least two of the sublayers are made of different materials .
[0095] In the above semiconductor device structure, it further includes: a first conductive layer located between the semiconductor substrate and the first capacitor dielectric layer; and a first conductive layer located between the first capacitor dielectric layer and the second capacitor dielectric layer. And a third conductive layer located above the second capacitor dielectric layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer Each serves as an electrode of the first capacitor or the second capacitor.
[0096] In the above semiconductor device structure, it further includes: a first conductive layer located between the semiconductor substrate and the first capacitor dielectric layer; and a first conductive layer located between the first capacitor dielectric layer and the second capacitor dielectric layer. And a third conductive layer located above the second capacitor dielectric layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer Each serves as an electrode of the first capacitor or the second capacitor, wherein at least one of the first conductive layer, the second conductive layer, and the third conductive layer has a range from 3.5 nm to Average particle size in the range of 6.5nm.
[0097] In the above semiconductor device structure, it further includes: a first conductive layer located between the semiconductor substrate and the first capacitor dielectric layer; and a first conductive layer located between the first capacitor dielectric layer and the second capacitor dielectric layer. And a third conductive layer located above the second capacitor dielectric layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer Each electrode used as the first capacitor or the second capacitor further includes: a first barrier layer located between the first conductive layer and the first capacitor dielectric layer; A second barrier layer between the conductive layer and the second capacitor dielectric layer; and a third barrier layer located above the third conductive layer.
[0098] In the above semiconductor device structure, it further includes: a first conductive layer located between the semiconductor substrate and the first capacitor dielectric layer; and a first conductive layer located between the first capacitor dielectric layer and the second capacitor dielectric layer. And a third conductive layer located above the second capacitor dielectric layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer Each electrode used as the first capacitor or the second capacitor further includes: a first barrier layer located between the first conductive layer and the first capacitor dielectric layer; A second barrier layer between the conductive layer and the second capacitor dielectric layer; and a third barrier layer located above the third conductive layer, wherein the first barrier layer, the second barrier layer and At least one of the third barrier layers has an average particle size in the range from 0.5 nm to 1.2 nm.
[0099] In the above semiconductor device structure, it further includes: a first conductive layer located between the semiconductor substrate and the first capacitor dielectric layer; and a first conductive layer located between the first capacitor dielectric layer and the second capacitor dielectric layer. And a third conductive layer located above the second capacitor dielectric layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer Each serves as an electrode of the first capacitor or the second capacitor, wherein the first conductive layer is thicker than the second conductive layer.
[0100] In the above semiconductor device structure, it further includes: a first conductive layer located between the semiconductor substrate and the first capacitor dielectric layer; and a first conductive layer located between the first capacitor dielectric layer and the second capacitor dielectric layer. And a third conductive layer located above the second capacitor dielectric layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer Each electrode used as the first capacitor or the second capacitor further includes: a first conductive structure electrically connected to the first conductive layer; a second conductive structure electrically connected to the second conductive layer And a third conductive structure electrically connected to the third conductive layer and the first conductive structure.
[0101] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a lower electrode located above the semiconductor substrate. The semiconductor device structure further includes a first capacitor dielectric layer located above the lower electrode and an intermediate electrode located above the first capacitor dielectric layer. The semiconductor device structure also includes a second capacitor dielectric layer located above the middle electrode. The second capacitor dielectric layer and the first capacitor dielectric layer are made of different materials. In addition, the semiconductor device structure includes an upper electrode located above the second capacitor dielectric layer.
[0102] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a lower electrode located above the semiconductor substrate. The semiconductor device structure further includes a first capacitor dielectric layer located above the lower electrode and an intermediate electrode located above the first capacitor dielectric layer. The semiconductor device structure also includes a second capacitor dielectric layer located above the middle electrode. The second capacitor dielectric layer and the first capacitor dielectric layer are made of different materials. In addition, the semiconductor device structure includes an upper electrode located above the second capacitor dielectric layer. The lower electrode, the first capacitor dielectric layer, and the middle electrode together form a first capacitor, and the middle electrode, the second capacitor dielectric layer, and the upper electrode together form a second capacitor. The first capacitor has a first linear temperature coefficient and a first squared voltage coefficient, and the second capacitor has a second linear temperature coefficient and a second squared voltage coefficient. One or both of the first ratio of the first linear temperature coefficient to the second linear temperature coefficient and the second ratio of the first squared voltage coefficient to the second squared voltage coefficient is negative.
[0103] In the above semiconductor device structure, wherein the first capacitor dielectric layer has compressive stress, and the second capacitor dielectric layer has tensile stress.
[0104] In the above semiconductor device structure, wherein the first capacitor dielectric layer has tensile stress, and the second capacitor dielectric layer has compressive stress.
[0105] In the above semiconductor device structure, wherein at least one of the lower electrode, the intermediate electrode, and the upper electrode has a particle size in a range from 3.5 nm to 6.5 nm.
[0106] In the above semiconductor device structure, it further includes: a first protective layer covering the sidewall of the upper electrode; and a second protective layer covering the sidewall of the intermediate electrode and the first protective layer.
[0107] In the above semiconductor device structure, further comprising: a first protective layer covering the sidewall of the upper electrode; and a second protective layer covering the sidewall of the intermediate electrode and the first protective layer, wherein the The first protective layer is in direct contact with the upper electrode and the second capacitor dielectric layer.
[0108] In the above semiconductor device structure, further comprising: a first protective layer covering the sidewall of the upper electrode; and a second protective layer covering the sidewall of the intermediate electrode and the first protective layer, wherein the The first protective layer is in direct contact with the upper electrode and the second capacitor dielectric layer, wherein the second protective layer is in direct contact with the first capacitor dielectric layer, the lower electrode and the first protective layer direct contact.
[0109] In the above semiconductor device structure, further comprising: a first conductive structure electrically connected to the lower electrode; a second conductive structure electrically connected to the middle electrode; a third conductive structure electrically connected to the upper electrode; A fourth conductive structure connected to the first conductive layer and the third conductive structure.
[0110] According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a lower conductive layer over the semiconductor substrate and forming a first capacitor dielectric layer over the lower conductive layer. The method also includes forming an intermediate conductive layer over the first capacitor dielectric layer and forming a second capacitor dielectric layer over the intermediate conductive layer. The second capacitor dielectric layer and the first capacitor dielectric layer are made of different materials. The method also includes forming an upper conductive layer over the second capacitor dielectric layer. One (or more) of the lower conductive layer, the middle conductive layer, and the upper conductive layer has an average particle size in a range from about 3.5 nm to about 6.5 nm.
[0111] In the above method, wherein the lower conductive layer, the intermediate conductive layer, and the upper conductive layer are formed using a sputtering process, at least one of the sputtering is performed at an operating temperature ranging from 100 degrees Celsius to 150 degrees Celsius. And the method further includes cooling the lower conductive layer, the middle conductive layer, and the upper conductive layer immediately after forming the lower conductive layer, the middle conductive layer, and the upper conductive layer.
[0112] The features of several embodiments are summarized above, so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and/or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention. .

PUM

PropertyMeasurementUnit
Average particle size3.5 ~ 6.5nm
Average particle size0.5 ~ 1.2nm

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