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10-tube memory cell with p-p-n and p-n-n hybrid structure

A P-P-N, storage unit technology, applied in the direction of information storage, static memory, read-only memory, etc., can solve the problems of read/write failure, susceptibility to noise interference, etc.

Active Publication Date: 2021-01-15
CHINA MARITIME POLICE ACADEMY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although the above-mentioned new types of memory cells can work at sub-threshold voltages, their minimum operating voltages are all around 0.4V, and they need read / write auxiliary circuits to help. Once the read / write auxiliary circuits are lost , they are easily disturbed by noise, causing read / write failures

Method used

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  • 10-tube memory cell with p-p-n and p-n-n hybrid structure
  • 10-tube memory cell with p-p-n and p-n-n hybrid structure
  • 10-tube memory cell with p-p-n and p-n-n hybrid structure

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Embodiment

[0012] Example: such as figure 1 As shown, a 10-tube memory cell adopting a P-P-N and P-N-N hybrid structure includes a bit line BL, an inverted phase line BLB, a word line WL, a write word line WWL, a P-N-N type inverter 1, a P-P-N type inverter 2 and Read and write selection circuit; P-N-N type inverter 1 includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3, the first MOS transistor M1 is a P-type MOS transistor, the second MOS transistor M2 and the third MOS transistor The tubes M3 are all N-type MOS tubes, the source of the first MOS tube M1 is connected to the power supply, the drain of the first MOS tube M1 is connected to the drain of the second MOS tube M2 and its connection terminal is the P-N-N type inverter 1 Output terminal, the output terminal of the P-N-N type inverter 1 is the first storage node T1 of the 10-tube storage unit, the gate of the first MOS transistor M1 is connected to the gate of the third MOS transistor M3 a...

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Abstract

The invention discloses a 10-tube memory cell with a P-P-N and P-N mixed structure, which comprises a bit line, an anti-phase line, a word line, a writing line and a P-N-N-type inverter, a P- P-N-typeinverter, and a read-write selection circuit; the P- N-N-type inverter comprises a first MOS transistor, a second MOS transistor and a third MOS transistor, the first MOS transistor is a P-type MOS transistor, and the P-p-N-type phase inverter comprises a fourth MOS transistor, a fifth MOS transistor and a sixth NMOS transistor. The read-write selection circuit comprises a seventh NMOS transistor, an eighth MOS transistor, a ninth MOS transistor and a tenth MOS transistor. The 10-tube memory cell has the advantages that the read-write noise tolerance is high, noise interference is not prone to occurring in the read-write process, and the stability is high.

Description

technical field [0001] The invention relates to a storage unit, in particular to a 10-pipe storage unit adopting a P-P-N and P-N-N hybrid structure. Background technique [0002] In modern chip design, low power consumption has become an equally important design goal as area and performance. Reducing the working voltage of the chip is the most direct and effective way to reduce the power consumption of the chip. However, too low working voltage will not only affect the performance of the chip, but also reduce the stability of the working of the chip. As one of the important components of the chip, the memory usually dominates the power consumption of the entire chip, and its operating voltage has become a bottleneck to reduce the operating voltage of the chip. [0003] 6T-SRAM has been working for the entire IC industry for many years as the most commonly used memory technology. 6T-SRAM adopts classic 6-tube memory cell structure, which makes the entire SRAM have a very sm...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/04G11C16/30
Inventor 温亮卢艳孟春宁吕建平路士兵赵强漆世钱
Owner CHINA MARITIME POLICE ACADEMY