10-tube memory cell with p-p-n and p-n-n hybrid structure
A P-P-N, storage unit technology, applied in the direction of information storage, static memory, read-only memory, etc., can solve the problems of read/write failure, susceptibility to noise interference, etc.
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[0012] Example: such as figure 1 As shown, a 10-tube memory cell adopting a P-P-N and P-N-N hybrid structure includes a bit line BL, an inverted phase line BLB, a word line WL, a write word line WWL, a P-N-N type inverter 1, a P-P-N type inverter 2 and Read and write selection circuit; P-N-N type inverter 1 includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3, the first MOS transistor M1 is a P-type MOS transistor, the second MOS transistor M2 and the third MOS transistor The tubes M3 are all N-type MOS tubes, the source of the first MOS tube M1 is connected to the power supply, the drain of the first MOS tube M1 is connected to the drain of the second MOS tube M2 and its connection terminal is the P-N-N type inverter 1 Output terminal, the output terminal of the P-N-N type inverter 1 is the first storage node T1 of the 10-tube storage unit, the gate of the first MOS transistor M1 is connected to the gate of the third MOS transistor M3 a...
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