combined heuristic instruction selection optimization method for VLIW basic block scheduling

Abstract

The invention discloses a combined heuristic instruction selection optimization method for VLIW basic block scheduling, and the method comprises the steps: S1, carrying out the selection and transmission of an instruction in each instruction period, and carrying out the step S2 if at least one functional unit has the residual effective instruction stage number of 2; S2, obtaining an association function unit corresponding to each ready instruction, searching a first type of association unit with the residual effective instruction number being greater than 2, searching a second type of association unit with the residual instruction number being 2, obtaining the time required by the completion of the residual instruction, and determining to obtain a first heuristic quantity and a second heuristic quantity; and S3, selecting a ready instruction as a final output ready instruction according to the determined first heuristic quantity and second heuristic quantity. The method can improve theinstruction scheduling optimization effect when the number of the remaining instruction stages of the functional unit is small, and has the advantages of being simple in implementation method, good in scheduling optimization effect, high in execution efficiency and the like.

Description

technical field [0001] The invention relates to the technical field of compiling and optimizing VLIW (Very Long Instruction Word, Very Long Instruction Word) architecture processors, in particular to a combined heuristic instruction selection optimization method for VLIW basic block scheduling. Background technique [0002] Basic block scheduling is one of the important optimization processes to improve the parallelism of instructions. On the premise of ensuring the correct execution logic, it fully utilizes the performance of the hardware by rearranging the execution order of instructions. It is an important factor for the VLIW architecture to improve code execution efficiency. method. In basic block instruction scheduling, the core problem that affects the effect of instruction scheduling is the problem of instruction selection at each beat. [0003] For the pipeline architecture, the basic block scheduling usually adopts the table scheduling method, which is to maintain ...

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Problems solved by technology

[0008] In view of the characteristics of the vector VLIW architecture, in order to effectively use ready instructions to fill the delay slots of effective instructions, Chinese patent application CN104699466A provides a multi-heuristic instruction selection method for VLIW architecture, which realizes multi-heuristics based on instruction dependency priority In order to solve the instruction selection problem, the rich functional unit resources of the processor can be used to mine the parallelism of the basic block instruction sequence, but this method only starts from the perspective of releasing the scheduling domain of the associated functional unit, and does not consider the functional unit The time required to execute the remaining instructions, and the total execution time of the basic block instruction sequence depends on the time Te of the instructions in the last instruction execution package to be executed, when the remaining instructions to be scheduled in some (or all) functional units depend on Applying this method when the number of priorities is small will result in a decrease in scheduling optimization performance, and cannot effectively ensure a better scheduling effect

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