How nldmos is made

Abstract

The invention discloses a manufacturing method of NLDMOS. The body region forming step includes: forming a first photoresist pattern with a first opening defining a P-type body region. Etching is performed to expose the surface of the deep N well, and the first side of the polysilicon gate formed after etching has a second opening. Perform ashing treatment on the first photoresist pattern; the ashing treatment removes the surface part of the first photoresist pattern formed with polymer on the surface and expands the first opening into a third opening, and the second and third openings A polysilicon protruding portion composed of the first polysilicon layer is formed between them. Ion implantation of the P-type body region is performed. Rapid thermal annealing is performed after removing the first photoresist pattern. The gate structure is formed by photolithography. A spacer is formed on a side of the gate structure. N-type heavily doped source and drain implants are performed to form source and drain regions. The invention can eliminate the bad effect of the polymer in the implantation of the P-type body region, so that a good channel can be formed and the length of the channel can be well controlled.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a NLDMOS manufacturing method. Background technique [0002] The process of simultaneously bipolar junction transistor (BJT), CMOS device and DMOS device on the same chip is a BCD process, such as figure 1 As shown, it is a schematic structural diagram of a switch type (Switch) NLDMOS in the existing BCD process, that is, an N-type LDMOS (laterally diffused metal oxide semiconductor). The switch type NLDMOS is usually also referred to as SNLDMOS for short; NLDMOS mainly includes: An N-type buried layer (NBL) 102, a P-type buried layer (PBL) 103, and a deep N well (DNW) 104 are formed on it; a high-voltage P-well (HVPW) 105 is formed on the top of the P-type buried layer 103, and a high-voltage P-well (HVPW) 105 is formed in the high-voltage P-well 105 There is a low-voltage P well (LVPW) 107, a P+ region is formed on the top surface of the low-vo...

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Problems solved by technology

exist Figure 2A In the corresponding ion implantation 203 of the P-type body region 109, during the process of etching the polysilicon layer 111 to form the first side of the polysilicon gate 111, a polymer (polymer) will be generated and the polymer will adhere On the surface of the photoresist pattern 201, this will make it impossible for the ion implantation 203 in some regions to implant impurities into the inside of the first side surface of the polysilicon gate 111 along the width direction of the channel, so that the formation of the The channel, that is, the channel must be formed by inversion of the surface of the covered P-type body region 109 through the polysilicon gate 111, and the ion implantation 203 cannot implant impurities into the first layer of the polysilicon gate 111. When the side is inside, the channel cannot be formed, which will lead to SLDMOS failure

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