Word line ladder lifting device and method for relieving reading disturbance by using word line ladder lifting device

Abstract

The invention provides a word line ladder lifting device and a method for slowing down reading disturbance by using the word line ladder lifting device. The word line ladder lifting device comprises an inverter, a PMOS transistor and an NMOS transistor, the input end of the inverter is connected with an input signal, and the output end of the inverter, the source electrode of the PMOS tube and thegrid electrode of the NMOS tube are connected with word lines; the drain electrode of the PMOS transistor is connected with the drain electrode of the NMOS transistor; the grid electrode of the PMOStube is connected with the output end of an NOT gate; the bit line tracking unit is connected with one input end of the NOT gate. When no external enable signal is input, the number of units of the bit line tracking unit is changed, so that the working time of the elevator is prolonged, and the reading disturbance and the half-selection disturbance are reduced; when an external enable signal is input, the number of units of the bit line tracking unit is adjusted by comparing the charging and discharging time length of the input signal of the bit line tracking unit with the charging and discharging time length of the external enable signal, so that the reading disturbance and half-selection interference of the step-up transformer are reduced, the unstable type of the circuit under low-voltage operation is reduced, and the low yield is avoided.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a word line lifter and a method for using the word line lifter to slow down reading disturbance. Background technique [0002] Static random-access memory (Static Random-Access Memory, SRAM) is widely used in (system on a chip, SoC) and processor caches, and it also accounts for most of the chip area. Due to power and other reasons, the minimum chip voltage Vmin is limited. Static access memory uses the most stringent design rules, so it is very sensitive to changes in process, voltage, temperature, etc. The circuit technology that has been proposed so far can reduce the word line technology. This technology mainly reduces the disturbance generated during reading and the half select disturbance (half select disturbance), but this technology will reduce the ability to write at low voltage. [0003] Therefore, it is necessary to propose a new word line lifter and a method for...

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Problems solved by technology

[0004] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a word line lifter and a method for slowing down read disturbances using the word line lifter, which are used to solve the problem of slowing down read disturbances in the prior art. The disturbance and half-selection disturbance generated during the low voltage reduce the writing ability

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