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Array substrate preparation method and array substrate

A technology of array substrate and base substrate, which is applied in the field of array substrate and array substrate preparation, can solve the problem that the line width of photoresist and the spacing of metal wiring cannot be taken into account.

Active Publication Date: 2019-07-23
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Aiming at the above-mentioned deficiencies in the prior art, the present invention provides a method for preparing an array substrate, that is, an array substrate, to at least partially solve the problem that the line width of the exposed photoresist and the line spacing of the metal wiring cannot be balanced

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  • Array substrate preparation method and array substrate

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Embodiment Construction

[0027] The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0028] The following combination figure 1 and Figure 2a-Figure 2c , detailing the preparation method of the array substrate of the present invention. like figure 1 As shown, the present invention provides a method for preparing an array substrate, the method comprising the following steps:

[0029] Step 11, adjusting the temperature of the first electrode in the reaction chamber to a preset temperature capable of slowing down the ashing speed of the photoresist.

[0030] Specifically,...

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Abstract

The invention provides an array substrate preparation method and an array substrate. By adjusting the temperature of a first electrode carrying the substrate to a preset temperature, in the process ofetching a metal film with process gas, a small portion of the photoresist layer melts and peels off, in the region, not covered by the photoresist layer, of the metal film, a protective layer is formed on the side wall of a recessed portion formed by etching, and the protective layer can ensure that the side wall of the formed recessed portion is not further etched during the etching process, andthe temperature of the first electrode is maintained at the preset temperature during the etching process, so that the protective layer is not rapidly ashed. In this way, after the etching is completed, the wire width of the metal trace is larger than the width of the region reserved before the etching for coating the photoresist, so that the wire width of the exposed photoresist layer can be reduced, and the wire spacing of the metal trace can be correspondingly increased, thereby avoiding the occurrence of short circuit, and the wire width of the metal trace after etching at the same time can also meet the design requirements.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a method for preparing an array substrate and the array substrate. Background technique [0002] With the development of display technology, the resolution of display devices is getting higher and higher, and the size of thin film transistors is getting smaller and smaller. Under the condition of ensuring a certain line width, the line spacing will become smaller and smaller. Due to the limitation of the resolution of the exposure machine, when the line spacing is reduced to a certain extent, the exposure of the photoresist at the position of the line spacing will be incomplete, and there will be photoresist residue after development, and the metal traces will be etched insufficiently, which will easily lead to short circuits and trigger points. The thread is bad. If in order to ensure that the line spacing is large enough, correspondingly, the line width of the exposed...

Claims

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Application Information

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IPC IPC(8): H01L21/77H01L27/12H01L21/3065
CPCH01L21/3065H01L27/124H01L27/1259
Inventor 许家豪宋亮赵吾阳季雨菲程浩
Owner BOE TECH GRP CO LTD
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