GOA circuit structure and driving method

Abstract

The invention discloses a GOA circuit structure and a driving method. The GOA circuit structure comprises a pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit and a pull-down maintaining unit. The pull-up control unit and the bootstrap unit control a control node of the nth GOA unit to be located at a first high potential and a second high potential in sequence. The pull-downunit outputs a gate driving signal according to the potential change of the control node and a high-voltage direct-current signal, and the GOA circuit structure can enable the pulse width of the gatedriving signal to be doubled, so that the pixel pre-charging time is prolonged.

Description

[0001] 【Technical field】 [0002] The invention relates to the display field, in particular to a GOA circuit structure and a driving method. [0003] 【Background technique】 [0004] The GOA (Gate Driver On Array) circuit is an important part of the liquid crystal display device. Using the existing thin-film transistor liquid crystal display Array process, the Gate row scan drive signal circuit is fabricated on the Array substrate to realize a progressive scan drive for the Gate. technology. [0005] Existing GOA circuits generally include a plurality of cascaded GOA units, and each level of GOA units corresponds to driving one level of horizontal scanning lines. The main structure of the GOA unit includes a pull-high circuit, a pull-up control circuit, a pull-down circuit, a pull-down holding circuit, and a bootstrap ( Boast) capacitors, etc., the pull-up control circuit can also be called a pre-charge circuit. The pull-up circuit is mainly responsible for outputting the clo...

AI Technical Summary

Problems solved by technology

[0006] However, for the GOA circuit set in a high-resolution and high-frequency (120HZ) LCD panel, due to the short charging time, the RC Loading of the gate line is heavy, resulting in the gate pulse signal (GatePulse ) The distortion (Distortion) is very serious, that is, the value of the falling time (Falling Time) of the Gn output signal is relatively large, resulting in a high risk of mischarging

In order to avoid the risk of wrong charging, the existing technology will lengthen the time from the gate line transition time point to the data transition time point, so the actual charging time is shorter, resulting in insufficient charging capacity

[0007] The current common method is to increase the number of clock signals (CK) to widen the output pulse of the gate, but due to the limitation of the border size of the panel, this method is difficult to achieve

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